set_clock_uncertainty shrinks the setup margin and also shrinks the hold margin: it reduces the setup required-time window and increases the hold requirement, so slack falls on both checks. Its contents depend on how much of the clock the tool already knows.
Flow stage | Clock model | Uncertainty should include |
|---|---|---|
Synthesis, early floorplan | Ideal (no skew known) | Expected skew + jitter + margin |
After clock tree synthesis | Propagated (real latencies) | Jitter + a small margin (skew is now measured) |
Signoff | Propagated, with variation derates | PLL jitter and any signoff margin required by the process |
The table below compares one path with and without setup uncertainty. The margin alone flips the sign of the slack.
Quantity | Without uncertainty | With 0.15 ns setup uncertainty |
|---|---|---|
Period | 2.00 ns | 2.00 ns |
Clock-to-Q + logic | 0.35 + 1.45 = 1.80 ns | 1.80 ns |
Setup | 0.12 ns | 0.12 ns |
Uncertainty | 0 | 0.15 ns |
Slack | 2.00 − 0.12 − 1.80 = +0.08 ns | 2.00 − 0.12 − 0.15 − 1.80 = −0.07 ns |
For a same-edge hold check from a common clock source, correlated source jitter can cancel between launch and capture. Setup usually compares different edges, so cycle-to-cycle jitter can remain. Derive each uncertainty from the actual edge relationship, source correlation and residual jitter assumptions; unrelated clocks do not inherit common-source cancellation. Hold-fix area is not a reason to reduce a required margin.
Values such as -setup 0.15 and -hold 0.05 are illustrative, in ns, not recommended defaults. Record the PLL specification, correlation assumptions and flow-owned margin budget; avoid counting variation or propagated skew twice.
No: 0.05 − 0.15 = −0.10 ns. It needs 0.10 ns more of improvement before the clock tree exists.
The values -setup 0.15 and -hold 0.05 are teaching numbers in ns, not recommended defaults.