Some paths need more than one cycle, and some are never active. Timing exceptions record these guarantees, and each one needs an RTL reason plus a test.
Read the tree from the top and stop at the first yes. Each question asks for something the RTL or the mode must guarantee, not something the timing report shows.
Mode constants come first: case analysis changes what STA sees instead of removing a check.
A clock-domain crossing is never solved by an exception alone; the synchroniser comes first.
The last box is the most common answer. Most failing paths are real and need a timing fix.
4 lessons, about 20 min
Capture occurs three full periods after the corresponding launch, and the source operands hold throughout that window. Checking capture frequency alone is insufficient: its phase relative to launch matters. Check both promises.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Taxonomy and Intent
Multicycle, false path, case analysis, disable timing and min/max delay each answer a different question about the path.
Use the smallest -from and -to, one reason per exception, and review setup and hold together.
A failing output path is a real requirement, not a false path.
Rule of thumb: review an exception like code: name the RTL that guarantees it and back it with a test.
Multicycle Setup and Hold Pairing
-setup N moves the setup edge to n+N. The hold edge follows to n+N-1, and -hold N-1 puts it back at n.
The cadence must give at least N periods between launch and capture. Both enables repeating every three edges is not enough if their phase gives one.
The number N comes from the RTL. If you cannot read N from it, you do not have a legal multicycle path.
Rule of thumb: a multicycle number must be large enough for the logic and true in the RTL cadence.
RTL Pattern That Often Needs MCP
Operand registers change only on an accepted start. A counter or FSM says when the result captures, and a clock enable makes it sample only then.
The constraint starts at the operand registers, never at the module inputs, because the registers freeze the data for the whole window.
Do not use y as a multicycle end point if other logic also writes it or reads its input path in one cycle.
Rule of thumb: pipeline for throughput; use a multicycle path only when the control can wait and the operands are stable.
False Paths and Case Analysis
A false path needs an RTL reason and proof. A configuration register is false only with a settling contract, such as 20.00 - 0.35 - 12.00 - 0.15 = 7.50 ns margin.
Scope a reset false path to the synchroniser's asynchronous pins. The synchronised reset keeps recovery and removal checks.
Never apply case analysis to a signal that changes at run time.
Rule of thumb: if a path crosses clock domains, a false path is not a fix: you still need a synchroniser, handshake or FIFO.
Mini project: close timing on an 8-tap FIR filter
Code lab: Timing exception path
Code lab: Multi-cycle divider step
Interview: run a mock interview on this topic