Sequential Design

What this section covers

Sequential RTL adds state over time : registers, counters, pipelines, and flow control. Mastery here unlocks timing closure (Part 5) and FSM control (Part 4).

Topics in this section

1. Flip-flops & registers — templates and reset

2. Counters & timers — modulo and Gray counters

3. Shift registers & LFSR — serializers and PRNG

4. Pipelining — throughput vs latency

5. Stalls & bubbles — backpressure without breaking timing

6. Retiming — moving logic across register boundaries

Pipeline sketch

D ──►|R0|──►|R1|──►|R2|──► OUT
        stall?  bubble?  skid?
              │
        Part 5 STA closes each stage delay

Key takeaways

• Non-blocking assignments in always_ff — blocking in always_comb.

• Pipeline depth trades latency for MHz — revisit with rtl/timing/sta-intro.

• Stall/bubble patterns recur in Part 7 valid/ready buses.

Related topics

• Combinational overview (logic between FFs)

• Pipelining

• STA intro (close pipeline stages)

• Setup/hold/slack

• Controller/datapath FSM

• Sequential/pipeline interview

Deep dive

This lesson deepens Sequential Design within sequential. Senior reviewers expect you to connect mechanism to register templates, pipelines, and flow control — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: reset complete, NBA in flops, pipeline latency documented. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

SEQUENTIAL DESIGN

  inputs ──► [sequential] ──► mechanism ──► outputs
                │                │
           sequential     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// sequential/sequential: Sequential Design
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Pipeline stall vs bubble — when each?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Sequential Design": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Sequential Design : Counter skips values after reset — verify sync release and enable gating.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Pipeline latency check
repeat (PIPE_LAT) @(posedge clk);
check_exp(dut_out);

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Sequential Design". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.