Sequential logic stores state across clock edges in registers with next-state logic and reset. This section covers flip-flops, counters, shift registers, pipelining, flow control, and retiming.
Topic | Lessons | After it you can… | Study time |
|---|---|---|---|
5 | Write registers with the right reset and enable style. | 2 h | |
6 | Build up/down counters, prescalers and a watchdog. | 2 h | |
3 | Serialize and deserialize data; generate PRBS sequences. | 2 h | |
5 | Pipeline a datapath, add valid/ready flow control, and build a pipelined MAC with its precision checks. | 3–4 h | |
5 | Stall, flush, forward, and share a port fairly with a round-robin arbiter. | 2–3 h | |
3 | Balance stages and cut the ready path with a skid buffer. | 2 h |
Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.
Valid bits decide whether a stage holds real work, so they must start at 0. Data registers are overwritten before they are used, so a reset only adds area and timing cost.
Use these four questions to decide whether you are ready to move on: explain, predict, implement and debug. If one is shaky, each answer names the lesson to revisit. New readers can skip this until they finish the section.
A clock enable is a mux in front of D: the flop still sees every clock edge but reloads its own value when disabled, so the clock tree is untouched. A gated clock puts logic on the clock path, which adds skew and can glitch. RTL writes an enable and lets the tools insert a proper integrated clock-gating cell. Revisit Clock enable vs gated clock.
Throughput is one result per cycle: 500 million results per second. Latency is three cycles, 6 ns, from an input to its result. Pipelining raised the clock rate the logic allows; it did not shorten the time for one item. Revisit Throughput and latency.
en is high, wraps to 0, and raises tc for one enabled cycle at N-1.always_ff @(posedge clk) if (!rst_n) cnt <= '0; else if (en) cnt <= (cnt == N-1) ? '0 : cnt + 1'b1; and assign tc = en && (cnt == N-1);. Gating tc with en makes it last exactly one counting step. Revisit Up/down counter with terminal count and reload.
in_valid is high. What is wrong?It loads without a handshake, so a new word overwrites one that has not left yet. Load only when in_valid && in_ready, with in_ready = !out_valid || out_ready: the stage accepts only when it is empty or its word is leaving in the same cycle. Revisit Valid/ready pipeline flow control.
Complete modules are compiled and self-checking testbenches are run by separate validation commands, not on every build.
Pipelines and handshakes are tested with random stalls and a scoreboard, so ordering, loss and duplication are checked on thousands of items.
Waveforms in these lessons come from real simulation output; structure diagrams are drawn by hand.