A datapath holds and transforms data while a controller decides what happens each cycle. The two meet at a short list of control signals and status flags.
6 lessons, about 24 min
a > b; the decision “subtract a−b now”?Datapath: the operand registers and the comparator (it produces a status flag). Controller: the states and the decision to subtract (it drives a control signal).
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Split Design: Intent First
Variables become registers, operations become functional units, conditions become status flags.
The controller sends controls down; the datapath reports flags up.
States exist where time passes, not at every line of pseudo-code.
Signal Contract Between FSM and Datapath
Exactly one block drives each register. Neither side reads the other's internal registers.
Controls are valid for one cycle and the datapath acts at the next edge.
If the datapath needs two cycles, add a ready status signal instead of assuming timing.
Two-Process FSM Style
The clocked process holds state <= next with reset; the combinational process decides next state and outputs.
Name states after what the machine does, not S0 and S1.
Specify the observation edge before comparing the latency of two styles.
Coding Rules That Prevent Latent Bugs
Default every output and next at the top of the combinational block.
Give the case a recovery default, and reset the state register to a legal state.
One driver per signal; the unique keyword does not make a default a don't-care.
Worked Example: GCD
IDLE loads on start, RUN subtracts the smaller from the larger, and DONE reports the result.
This listing needs both inputs at least 1; with one zero operand subtraction makes no progress.
The subtract algorithm needs up to max(a,b) iterations.
FSM Bug Stories
A Mealy output is only as clean as the inputs it decodes: qualify it with valid or enable.
Write what a counter means at the compare (beats already sent), and the exit value follows.
A lock-up starts before the hang: the release event arrived in a state that does not test it.
Rule of thumb: find the first wrong slot, then ask which state and which input made it.
Mini project: an SPI master, controller and datapath
Practice question: How state transitions are handled in Verilog FSMs
Practice question: Safe state machine with illegal-state recovery
Practice question: Incomplete case and unique0: simulation vs synthesis
Code lab: Handshake FSM
Interview: run a mock interview on this topic