Some operations are too large for one clock period. A sequencer spreads them over several cycles, trading latency for area and clock speed.
Operation | One cycle | Sequenced |
|---|---|---|
8×8 multiply | A full array of adders | One adder, 8 steps (this topic) |
Memory read | Not possible if the RAM has latency | Issue, wait, capture |
Division, CRC over a block, packet parsing | Large combinational logic | A loop in an FSM |
4 lessons, about 17 min
The sequenced version is much smaller (one adder and a few registers) but done is observed 9 edges after acceptance, and a new multiply can start only every 10 cycles. The array multiplier has one-cycle throughput but uses roughly 8 adders' worth of logic with a long combinational path.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
The Sequencer Mindset
Capture the operands in registers on start, because the caller may change the inputs during the operation.
Pin down done: a pulse or a level, and whether the result is valid in the same cycle or the next.
Load N and count down to zero when N varies. A zero-detect is cheaper than a comparison with a stored N.
Rule of thumb: write the cycle table before the states.
Shift-Add Multiply
Acceptance is edge 0, iterations run at edges 1 to W, and the product and done follow edge W. The earliest next acceptance is edge W + 2.
done marks a valid product, and !busy marks readiness for a new operation. They are different signals.
The multiplicand register must be 2W bits wide, or the high bits are silently dropped.
Rule of thumb: count latency from the acceptance edge and say which edge a consumer samples on.
Memory Read Sequencer with Latency
Issue the address, wait L - 1 cycles, then capture. Data is available L + 1 periods after acceptance and the consumer samples at L + 2.
Register done together with the data. A combinational done can announce a result a cycle before the data register holds it.
Make the latency a parameter and test several values.
Rule of thumb: if the RAM output register changes, the sequencer's latency parameter changes with it.
Sequencer Robustness
Wait for rvalid rather than counting cycles, and bound every wait with a timeout or a proof of termination.
A timeout is a failure report. The ERR state keeps busy high until the peer is quiet and recover is asserted.
DRAIN absorbs a late answer after an abort. Without it, the aborted word lands in the next read.
Rule of thumb: design for the whole protocol, not only the happy path.
Mini project: an SPI master, controller and datapath
Practice question: Waveform debug of a write transaction timeout
Interview: run a mock interview on this topic