A memory controller hides RAM timing behind a simple request interface. It latches each request, waits out the read latency, and returns read data.
4 lessons, about 16 min
A read returns after acceptance; writes have no response. The response is a one-cycle pulse with no rsp_ready: the consumer must always capture it at the edge where rsp_valid is high. Later pickup needs a holding register/FIFO or a response ready/valid extension.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Objective and Interface
One request at a time, through valid/ready. A write drives the RAM for one cycle. A read waits for the RAM latency and then gives a one-cycle rsp_valid.
req_ready is a pure function of the state register, so it is safe to connect to any requester.
Writes give no response. The return of req_ready is their completion.
Rule of thumb: more throughput means a pipelined controller with a queue, not a faster single-request FSM.
State Machine and Bus Behavior
Writes finish in ACCESS. Reads go on through WAIT and end with one RESP cycle.
rsp_rdata is a plain wire from mem_rdata. It is valid only in the RESP cycle, so capture it on rsp_valid.
Only an enabled read (mem_en and not mem_we) launches data into the RAM's output pipeline.
Rule of thumb: use rsp_rdata only when rsp_valid is high.
Request Latching
Copy req_we, req_addr and req_wdata into we_r, addr_r and wdata_r at the accept edge, and use only the copies.
A driver that holds the old request until the controller is idle hides all three latch bugs. Change the inputs as soon as that is legal.
A correct but slower design can pass a value-only scoreboard, so also check the response edge.
Rule of thumb: the accept edge is the last moment the requester has to hold its request.
Design Closure Checklist
Cover all four states and transitions, write then read on the same address, and request changes on the cycle after accept.
Assert: rsp_valid follows only a read, exactly one rsp_valid per read, and mem_en only in ACCESS.
A formal proof covers the specified model under assumptions: progressing clock, stable offers, legal parameters and a fixed-latency RAM.
Rule of thumb: define in the interface that a reset cancels all outstanding requests.
Mini project: an SPI master, controller and datapath
Practice question: Design a burst access controller with a ready/valid handshake
Practice question: FSM verification strategy: coverage and assertions for corner cases
Interview: run a mock interview on this topic