Combinational Design

What this section covers

Combinational logic is every logic cone between registers . This section covers building blocks, delay intuition, arithmetic width rules, and the patterns that keep synthesis from inferring latches.

Topics in this section

1. Overview — delay, cones, and design partitioning

2. Mux / decoder / encoder — selection and address decode

3. Arithmetic — adders, multipliers, width extension

4. Comparators & shifters — compares and bit manipulation

5. Tri-state & buses — shared wires and bus holders

6. Latch inference — complete assignment and lint habits

Combinational cone (mental model)

INPUTS ──► [logic levels] ──► OUTPUTS
              │         │
         mux/select   arithmetic
              │
         every path must resolve (no latch)

Key takeaways

• Combinational depth drives cycle time — pair with Part 5 timing after Part 3 pipelines.

• Latch inference is the #1 combinational bug — defaults in always_comb matter.

• Arithmetic width mistakes show up again in Part 3 counters and Part 9 interviews.

Related topics

• Digital logic (Boolean base)

• Number systems (signed width)

• Pipelining (register boundaries)

• Latch inference deep dive

• Combinational interview Q&A

Deep dive

This lesson deepens Combinational Design within combinational. Senior reviewers expect you to connect mechanism to logic depth, latch inference, and arithmetic width — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: no latches, ref model matches, delay intuition documented. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

COMBINATIONAL DESIGN

  inputs ──► [combinational] ──► mechanism ──► outputs
                │                │
           combinational     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// combinational/combinational: Combinational Design
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

How do you prove no latch was inferred?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Combinational Design": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Combinational Design : Tri-state bus contention in sim — identify two drivers; replace with mux model for ASIC.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Exhaustive 3-input truth table
for (int a=0; a<2; a++)
  for (int b=0; b<2; b++)
    for (int c=0; c<2; c++)
      check_ref(a,b,c);

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Combinational Design". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.