Digital logic studies Boolean functions and their physical cost. A synthesis tool does not read intent; it maps the Boolean equations in the RTL onto gates, and the shape of that gate network decides the speed and size of the design.
Here is a question to keep in mind while you work through the topic: majority of three (output 1 when at least two of a, b and c are 1) can be written with 12 literals or with 6. Which form does the tool build, and does the choice ever matter once it is synthesised?
Each lesson below covers one step of that flow. Notation used throughout: ab or a·b means AND, a+b means OR (not addition), and a′ means NOT. In Verilog these are a & b, a | b and ~a.
6 lessons, about 26 min
Go in order: algebra before gates answers the opening question, and later lessons reuse its majority function as a running example.
16 rows. Each row can output 0 or 1 independently, so there are 2¹⁶ = 65,536 distinct 4-input functions. The count grows doubly exponentially, which is why tools, not people, minimize large functions.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Algebra Before Gates
One minterm per output-1 row, ORed together, is the most direct route from table to equation.
Literals approximate area and levels approximate delay, long before a tool runs.
In equations + means OR; in Verilog + is addition. Use | for OR.
Rule of thumb: write the equation first, then draw the gates.
The Identity Toolkit
The one-liner a + a'b = a + b is worth recognising on sight.
The consensus term is redundant in steady state but can be the term that stops a glitch.
Boolean equivalence says nothing about glitches, X propagation or timing.
Rule of thumb: never trust the algebra until a loop over every input has agreed with it.
De Morgan Rules
Negating a group flips the operator and negates each member: (a·b)' = a' + b'.
NAND alone builds any function: tie its inputs for NOT, then use De Morgan for the rest.
Use ~ on vectors; ! tests the whole vector and is rarely what you mean.
Rule of thumb: convert active-low names to active-high at the block boundary, so the bubbles stay in one place.
Truth Tables as a Debug Anchor
A reference that copies the design's equation proves nothing. Write it in a different style from the specification.
Exhaustive testing is feasible to about 2^20 vectors; time a small sample before extrapolating.
Assigning x as a don't-care promises the case cannot occur; simulation shows x while hardware picks 0 or 1.
Rule of thumb: if the input space is small, test all of it.
K-Map Intuition
Gray-code labels make neighbours differ by one variable, so a group of 2^k cells cancels k variables.
Groups are rectangles of 1s (or don't-cares) in powers of two, and they wrap at the edges.
Mark a cell don't-care only if the system can never present that input, and check it with an assertion.
Rule of thumb: keep the variables that stay fixed in the group and drop the ones that change.
Implementation Trade-offs
The same function has many implementations; speed usually costs area and the reverse.
Synthesis rebalances plain AND, OR and XOR trees. Structure matters for carries, priority logic and late inputs.
A static-1 hazard is harmless to values in synchronous logic with margin, but it matters on clocks, async resets and latch enables.
Rule of thumb: never drive a clock, an asynchronous reset or a latch enable from raw combinational logic.
Mini project: a 4-bit ALU with flags and an exhaustive bench
Interview: run a mock interview on this topic