Five tools cover almost every simplification: complement, absorption in both forms, distribution, and consensus.
Name | AND form | OR form |
|---|---|---|
Identity | a·1 = a | a+0 = a |
Null (domination) | a·0 = 0 | a+1 = 1 |
Idempotent | a·a = a | a+a = a |
Complement | a·a′ = 0 | a+a′ = 1 |
Involution | (a′)′ = a | (a′)′ = a |
Commutative | a·b = b·a | a+b = b+a |
Distributive | a·(b+c) = ab + ac | a+(b·c) = (a+b)·(a+c) |
Absorption | a·(a+b) = a | a + a·b = a |
Absorption (variant) | a·(a′+b) = a·b | a + a′·b = a + b |
Consensus | (a+b)(a′+c)(b+c) = (a+b)(a′+c) | ab + a′c + bc = ab + a′c |
The second distributive law (a + bc = (a+b)(a+c)) has no analog in ordinary arithmetic. It surprises people the first time.
It is valid for Boolean values. It converts between product-of-sums and sum-of-products.
Simplify y = ab + ab′ + a′b.
Group the first two terms and factor out a: ab + ab′ = a(b + b′).
Use the complement identity: b + b′ = 1, so the group becomes a.
Now y = a + a′b. Apply the absorption variant a + a′b = a + b.
Result: y = a + b. Three terms with two literals each collapsed into a single OR gate.
The step a + a′b = a + b is the most useful one-liner in the list. It is worth recognizing on sight.
Do not trust the algebra blindly. An exhaustive equivalence check on two or three inputs costs nothing and catches slips.
A testbench is simulation-only code that drives and checks a design. Here logic declares a four-state signal, assign keeps an equation connected to its inputs, and the initial block runs once. Predict the four input pairs before reading the loop.
Loop i | i[1:0] | {a,b} | Expected a OR b |
|---|---|---|---|
0 | 00 | a=0, b=0 | 0 |
1 | 01 | a=0, b=1 | 1 |
2 | 10 | a=1, b=0 | 1 |
3 | 11 | a=1, b=1 | 1 |
{a,b} joins two one-bit signals; assigning i[1:0] drives one pair. #1 advances one simulation time unit so these continuous assignments settle; it is not a gate delay measurement. !== reports different four-state results, including a known-versus-X mismatch. The loop checks only the four known binary pairs, not all X/Z combinations. Its pattern is drive, settle, compare; the testbench lessons explain clocks and scheduling later.
module tb_equiv;
timeunit 1ns;
timeprecision 1ps;
logic a, b;
logic y_orig, y_simpl;
assign y_orig = (a & b) | (a & ~b) | (~a & b);
assign y_simpl = a | b;
int errors = 0;
initial begin
for (int i = 0; i < 4; i++) begin
{a, b} = i[1:0];
#1;
if (y_orig !== y_simpl) begin
$display("FAIL: mismatch for a=%b b=%b orig=%b simpl=%b", a, b, y_orig, y_simpl);
errors++;
end
end
if (errors == 0) $display("PASS: ab + ab' + a'b matches a + b for all 4 input combinations");
$finish;
end
endmoduleThe consensus theorem says the term bc in ab + a′c + bc is redundant. Whenever b and c are both 1, either a or a′ is 1, so one of the other two terms is already true.
A minimizer deletes it. In an asynchronous or glitch-sensitive circuit, that “redundant” term is exactly what prevents a glitch, which is why the implementation trade-offs lesson revisits it.
a′b + a′b′ = a′(b + b′) = a′, so y = a + a′, which equals 1. The output is constant 1 for every input. A synthesis tool would replace the whole block with a tie-high.