Senior & Interview

What this section covers

Senior RTL engineers close loops across power, test, physical, debug, and timing ECO . The interview block applies model-answer chains (mechanism → motivation → when-to-use → pitfall → example) across nine categories.

Topics in this section

1. Low-power RTL — clock gating, UPF awareness

2. DFT / scan — controllability and observability

3. Physical design awareness — floorplan hooks

4. Waveform debug — triage methodology

5. STA ECO — last-mile timing fixes

6. Interview — 9 categories · 54 sub-lessons

Senior closure loop

RTL change ──► sim ──► STA ──► CDC ──► tape-out readiness
     │           │      │       │
  debug      coverage  ECO   interview prep

Key takeaways

• Staff-level answers name trade-offs and evidence (sim, STA, silicon).

• Interview categories map to Parts 2–7 — cross-link while rehearsing.

• ECO and debug skills assume fluency in Parts 3 and 5.

Related topics

• Interview hub (start here)

• Setup/hold/slack

• Async FIFO

• STA ECO

• CDC/reset interview

• Timing/STA interview

Deep dive

This lesson deepens Senior & Interview within senior. Senior reviewers expect you to connect mechanism to power, DFT, debug, ECO, and staff-level trade-offs — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: evidence bundle: sim, STA, CDC, silicon correlation. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

SENIOR & INTERVIEW

  inputs ──► [senior] ──► mechanism ──► outputs
                │                │
           senior     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// model answer: mechanism -> trade-off -> example

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Walk through last timing ECO you performed.

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Senior & Interview": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Senior & Interview : Low-power island won't wake — verify isolation and retention sequence.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Wave marker: first failing cycle
$display("FAIL t=%0t sig=%h", $time, sig);

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Senior & Interview". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.