Senior engineers close the loop from RTL change through simulation, STA, CDC, DFT, equivalence, and physical implementation to tape-out readiness. This section adds explicit handoff, DFT readiness, and an integrated capstone to the existing closure and interview material.
Topic | Lessons | After it you can… | Study time |
|---|---|---|---|
4 | Cut switching with intent-driven gating, isolation, and retention. | 30 min | |
5 | Build scan chains and check test-mode integration. | 30 min | |
4 | Write partition-friendly RTL that avoids congestion hotspots. | 30 min | |
4 | Narrow failures by hierarchy and read latch, race, and protocol bugs. | 30 min | |
4 | Apply minimal-risk ECOs and escalate to RTL changes when justified. | 30 min | |
5 | Own reproducible QoR, equivalence, handoff, and ECO release evidence. | 2 h | |
3 | Deliver scan-friendly RTL and integrate test clocks, MBIST, JTAG, and compression hooks. | 90 min | |
8 | Integrate CSRs, streams, FIFOs, CDC, reliability, verification, constraints, and signoff. | 12–20 h | |
2 | Choose between architectures under uncertainty, then re-decide when the constraints change. | 2 h | |
9 | Give model answers with trade-offs across nine categories plus whiteboard code. | 5 h |
Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.
Trade-offs and evidence: simulation results, STA numbers, or silicon correlation. The STA and ECO topic practices the closure loop, and Interview Prep rehearses it across nine categories.
Use these four questions to decide whether you are ready to move on: explain, predict, implement and debug. If one is shaky, each answer names the lesson to revisit. New readers can skip this until they finish the section.
When the violation is architectural (too many logic levels, a long wire built into the micro-architecture), when it fails across many corners or paths, or when the ECO would cost more area or schedule than the change. Local, small violations are what sizing and buffering ECOs are for. Revisit When an RTL change is the right call.
In shift mode the enable may hold the clock off, so the flops do not shift and the chain breaks or those flops cannot be controlled and observed, and fault coverage drops. Clock gates need a test-enable override that forces the clock on in test mode. Revisit Test clocks, resets and modes.
Isolation cells that clamp the outputs to a safe value, controlled from the always-on domain. The sequence is: assert isolation, then power down; on power-up, restore power, wait until it is stable (and any retention is restored), then release isolation. Revisit Power domains and isolation intent.
Equivalence checking proves the logic functions match; it does not check timing, X behavior or initialization. Look at the annotated timing (a new hold or setup problem), uninitialized flops or X propagation that RTL simulation hid, and the reset sequence. Revisit Proving an ECO: equivalence and GLS.
Directed simulation checks the exercised traces; a PASS is limited to its assertions and stimulus. A listing alone is unexecuted evidence until its run is recorded.
Generated waveforms show sampled simulation behavior. Cycle-resolution views do not establish pulse width, analog timing or physical safety.
Exhaustive finite checks cover the enumerated input space; formal proof covers behavior under reviewed assumptions. Neither replaces mapped/routed timing, CDC implementation checks, power, DFT or physical signoff.