A flip-flop samples its D input at the clock edge. Data must be stable before the edge (setup) and after it (hold).
Check | Question | Depends on clock period? | Fix by |
|---|---|---|---|
Setup | Did the new data arrive early enough before the next edge? | Yes | Less logic, earlier launch branch or later capture branch, longer period |
Hold | Did the new data stay away until after this edge's window closed? | No | Add delay on the data path, reduce skew |
Moving the capture clock earlier reduces setup slack; moving the launch clock earlier increases it. Useful skew means changing the specified branch relative to the other one. Recheck incoming hold and outgoing setup paths after any clock-tree change.
6 lessons, about 23 min
No. For a full-cycle, same-edge register path, hold is checked against the same clock edge, so the period does not appear in the hold equation. Only delay on the data path or skew changes can fix it.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Core Equations and Slack
Setup checks the next edge with the late (max) data delay. Hold checks the same edge with the early (min) data delay.
A later capture clock gives setup more time and hold less.
Slack is the margin to the requirement: positive means met, zero just met, negative a violation by that amount.
Rule of thumb: positive skew helps setup and reduces hold slack.
Interpretation Shortcut
Setup scales with the clock period. Hold does not, and a hold violation is a short-path problem.
For a full-cycle same-clock path, minimum period is the target period minus the worst setup slack (2.0 ns with WNS -0.12 ns gives about 2.12 ns).
Do not compare slack across different constraint sets.
Rule of thumb: split the path into clock-to-Q, logic, wire, setup and skew before choosing a fix.
Worked Numeric Examples
The model uses 0.35 ns clock-to-Q, 0.12 ns setup and 0.06 ns hold.
Path 1 (1.64 ns of logic) fails setup, path 4 fails hold, and skew moves the slack of both checks in opposite directions.
A violated window drives the modelled output to X as a diagnostic. It does not predict silicon.
Rule of thumb: compute the slack by hand, then see whether the model agrees.
Example 1: Setup Failure
Each fix recomputes slack for the same path. Compare the side effects, not only the new slack.
Pipelining gives the most slack but changes latency and may need valid and flush control.
Useful skew moves the problem. Re-check the capture flop's outgoing setup paths and the incoming hold path.
Rule of thumb: look at the path report first: many levels, restructure or pipeline; high fanout, duplicate or retime.
Example 2: Hold Failure
New data takes 0.40 ns and the hold window ends 0.44 ns after the launch edge, so the path fails by 0.04 ns.
Only data-path delay or skew changes hold slack.
Clock tree synthesis and automatic hold fixing with delay cells handle most hold violations in the flow.
Rule of thumb: fix hold after the clock tree is built, not before.
Fix Strategy: Setup vs Hold
Fix setup first, structurally in RTL. Then build the clock tree and fix hold with delay cells.
Thousands of hold buffers hint at a skew or architecture problem.
Re-run both checks at all corners after each fix.
Rule of thumb: never close timing by loosening constraints you do not understand.
Mini project: close timing on an 8-tap FIR filter
Interview: run a mock interview on this topic