Sign and size. Negative is a violation. Calibrate its size against the actual library/path budget, not a universal gate delay. In an illustrative 2.0 ns cycle with 0.50 ns reserved for clock-to-Q, setup and uncertainty, 1.50 ns remains for logic/wire. At an assumed 0.10 ns per loaded level, that suggests 15 levels; real delays depend on slew, load, wire and corner. Neither -0.02 nor -0.80 ns alone determines the fix.
Setup or hold. Setup scales with the clock; hold does not. A hold violation is a short-path problem.
Time breakdown. For setup, split the delay into clock-to-Q, logic levels, wire, setup time, and skew. The path report lists each cell and its delay.
Its budget is 3T, so add 0.30 / 3 = 0.10 ns to T: 2.10 ns, not 2.30 ns. Conversely, a half-cycle path with −0.10 ns slack needs a 0.20 ns period increase if duty cycle remains 50%. Other paths still need checking.
Ask three questions in order: is every endpoint timed, is it setup or hold, and how deep is the path? The answers point to the first fix.
Follow the tree from the top. Each diamond is a question you can answer from the report; each box is the first thing to try.
The constraint question comes first because a missing clock makes every other number meaningless.
For setup, the level count separates a structural problem (pipeline, restructure) from a physical one (one slow cell, a long wire or a port).
For hold, the spread matters: many tiny failures point to skew the flow can fix; one large failure points to a skewed boundary in the design.
Each row of the table pairs a symptom with its likely cause and first fix.
What you see | Likely cause | First thing to try |
|---|---|---|
Setup, logic exceeds its calibrated budget (e.g. >15 levels at 0.10 ns/level in the illustrative 1.50 ns budget) | Too much logic in one stage | Pipeline or restructure the RTL; confirm actual cell/wire delays |
Setup, few levels but one cell very slow | High fanout or long wire | Duplicate the register or buffer the net |
Setup, endpoint is an input/output port | I/O constraint too tight or unregistered I/O | Register at the boundary; recheck the I/O budget |
Hold, tiny negative slack on many paths | Skew between nearby registers | Let the flow insert hold buffers; check the clock tree |
Hold, large negative slack | A shift register or direct register-to-register path across a skewed boundary | Check clock domains and clock gating; add delay |
Slack looks great but the report has unclocked endpoints | Missing clock definition | Fix constraints |
About 2.12 ns, i.e. 1 / 2.12 ns ≈ 472 MHz. Re-evaluate all constraints at that period; the estimate does not apply unchanged to other edge relationships.