This illustrative path carries 1.65 ns of logic with no skew, for -0.12 ns setup slack. It is the unskewed counterpart of path 2; simulated path 1 uses 1.64 ns to avoid an event coincidence and therefore has -0.11 ns slack.
Item | Value |
|---|---|
Clock period T | 2.00 ns |
Clock-to-Q | 0.35 ns |
Logic + wires (max) | 1.65 ns |
Setup requirement | 0.12 ns |
Skew | 0.00 ns |
Setup slack | 2.00 − 0.12 − 0.35 − 1.65 = −0.12 ns |
Each fix recomputes slack for the same path. Costs move elsewhere, so compare before choosing.
Fix | New slack | Cost / side effect |
|---|---|---|
Cut logic from 1.65 to 1.50 ns (restructure, fewer levels) | 2.00 − 0.12 − 0.35 − 1.50 = +0.03 ns | RTL effort; usually area increases |
Slow the clock to 2.20 ns | 2.20 − 0.12 − 0.35 − 1.65 = +0.08 ns | 500 → 454.55 MHz: 9.09 % lower frequency for a 10 % longer period. Improves this full-cycle path by 0.20 ns with fixed delays/skew; other constraints and remaining failures need rechecking. No same-edge hold benefit |
Useful skew: delay the capture clock by 0.30 ns | 2.00 + 0.30 − 0.12 − 0.35 − 1.65 = +0.18 ns | The capture flop's outgoing paths lose 0.30 ns; hold slack on the incoming path drops by 0.30 ns |
Pipeline: split logic 0.85 + 0.80 ns with a new register | Stage 1: 2.00 − 0.12 − 0.35 − 0.85 = +0.68 ns; stage 2: +0.73 ns | One more cycle of latency and one more rank of registers; both stages have large margin |
2.20 − 0.12 − 0.35 − 1.50 = +0.23 ns.