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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
    • STA Foundations
    • Setup, Hold and Slack
      • Core Equations and Slack
      • Interpretation Shortcut
      • Worked Numeric Examples
      • Example 1: Setup Failure
      • Example 2: Hold Failure
      • Fix Strategy: Setup vs Hold
    • Skew and Variation
    • Timing Exceptions
    • Clock Gating
    • RTL for Timing
    • Clock Architecture
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹Setup, Hold and Slack
  1. Topics
  2. RTL Design
  3. Timing & Clocking
  4. Setup, Hold and Slack
  5. Example 2: Hold Failure

Part 5 · Timing & Clocking · Intermediate

Example 2: Hold Failure

A path with negative 0.04 ns hold slack and the delay fixes that close it.

On this page

    Why this matters

    A hold violation cannot be fixed by slowing the clock, because the period is not in the hold equation. Direct flop-to-flop paths are the typical risk.

    After this lesson you can: compute a hold slack for a short path, list the fixes that move it, and explain why slowing the clock does not.

    Failing path

    Item

    Value

    Clock-to-Q (min)

    0.35 ns

    Logic + wires (min)

    0.05 ns (almost a direct flop-to-flop connection)

    Capture clock skew

    +0.38 ns (capture clock arrives later)

    Hold requirement

    0.06 ns

    Hold slack

    0.35 + 0.05 − 0.38 − 0.06 = −0.04 ns

    The new data takes 0.40 ns to arrive. The capture edge comes 0.38 ns after the launch edge, and the hold window lasts 0.06 ns more.

    The data arrives 0.04 ns before the window closes. It disturbs the value the same edge must capture.

    Hold failure and fix on one magnified time axis. The shaded stable window runs from 0.26 to 0.44 ns around the capture edge at 0.38 ns. New data at 0.40 ns lands inside it (-0.04 ns); with 0.20 ns of buffer delay it lands at 0.60 ns, after it (+0.16 ns).

    Read each row as the moment the next word reaches the capture flop. It must land to the right of the shaded window.

    • Before: the new word arrives at 0.40 ns, inside the window that ends at 0.44 ns, so the old word is overwritten too soon.

    • After: 0.20 ns of buffer delay moves arrival to 0.60 ns, clear of the window by 0.16 ns.

    • The clock period is not on this axis at all. The window belongs to the same edge, which is why slowing the clock cannot move it.

    Direct flop-to-flop connections are the typical hold risk, since logic delay is near zero. Clock tree synthesis and automatic hold fixing with delay cells handle this in the flow.

    Avoid intentionally skewed clocks, such as gated or divided clocks, between directly connected flops.

    Fix options

    Only data-path delay or skew changes move hold slack. The clock period does not appear in the equation.

    Option

    Effect on hold slack

    Works?

    Slow the clock

    None (period is not in the equation)

    No

    Insert 0.20 ns of delay on the data path (hold buffers)

    −0.04 → +0.16 ns

    Yes, and it reduces setup slack by 0.20 ns (large here: 1.86 → 1.66)

    Reduce skew (rebalance the clock tree)

    Each 0.1 ns of skew removed adds 0.1 ns

    Yes, but a clock-tree change affects many paths

    Put combinational logic that is already needed on the path

    Adds its delay

    Yes, if the function needs it

    Use a flip-flop with larger clk→Q or a slower cell

    Adds a little

    Rarely a good choice

    Common mistakes

    Common pitfall

    Hold buffers add area and power, and they add delay on the path in every corner. Fixing hold by hand early on, before clock tree synthesis, usually gets undone or becomes unnecessary: wait until the clock tree is built.

    Interview

    “Why can't you fix a hold violation by slowing the clock?” For a full-cycle, same-edge register path, the hold check is between the launch edge and the same capture edge, so the period never appears in the equation. Opposite-edge paths and multicycle paths without a matching hold exception are the cases where hold does move with the period.

    Check yourself The same path gets 0.20 ns of delay buffer. What is the new setup slack if it was +1.86 ns before?

    1.86 − 0.20 = +1.66 ns. Plenty of margin remains, which is why hold fixing is usually safe on short paths.

    Remember

    • New data takes 0.40 ns and the hold window ends 0.44 ns after the launch edge, so the path fails by 0.04 ns.

    • Only data-path delay or skew changes hold slack.

    • Clock tree synthesis and automatic hold fixing with delay cells handle most hold violations in the flow.

    Rule of thumb: fix hold after the clock tree is built, not before.

    Keep going

    • Interview: run a mock interview on this topic

    Related topics

    • Fix strategy

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    See also

    • Core Equations and Slack
    • Interpretation Shortcut
    • Worked Numeric Examples