A clocked flip-flop burns power on its clock pin and tree wiring every cycle, even when its data does not change. Clock gating removes the clock from idle groups of flops. This topic models positive-edge flops behind a low-transparent latch/AND ICG. Other approved clock-control cells and dedicated FPGA clock resources can also be safe; use the target library/resource and its timing contract.
Each slot is one clock edge, rising (h) or falling (l), sampled just after it. The picture covers six clock periods.
clk toggles in all 12 slots. Every one of those toggles charges and discharges the clock pins it drives.
en falls in slot 3, while clk is low, and rises again in slot 9.
gclk toggles in slots 0 to 3 and 10 to 11 only: 6 toggles instead of 12. The three rising edges in between never reach the flops.
q counts 1, 2 and holds 2 through the gated-off edges, then counts to 3 at the first enabled edge. The register keeps its value without being clocked.
5 lessons, about 23 min
Mainly the clock network and the flop's clock-pin switching. Data-path power drops only indirectly (because the flop does not change). Gating high in the tree saves the most because it stops all the buffers below the gate.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Why Clock Gating Saves Power
Clock power is alpha x C x V^2 x f with alpha = 1 for an ungated clock. State the activity convention to avoid a factor of two.
One ICG per flop usually costs more than it saves. A gate for 8 to 64 flops, or higher in the tree, pays off more.
Net saving is avoided clock power minus the ICG, enable logic and extra CTS overhead. It can be negative.
Rule of thumb: measure activity first, then gate a group that is idle often and has an early enable.
The ICG Cell
A change of enable while the clock is high cuts a pulse short (1 to 0) or starts a late partial pulse (0 to 1).
The ICG latch is transparent while the clock is low and opaque while it is high, so the enable only matters at the start of a pulse.
In a real flow you instantiate the library ICG cell. You do not write the latch and AND by hand.
Rule of thumb: never gate a clock with a bare AND gate; use an integrated clock-gating cell.
Safe RTL Gating Style
Write a plain enable by default. Synthesis can replace the feedback mux with a clock gate where it pays off.
An explicit gate uses the library ICG through a wrapper, a registered enable and a test enable (te).
A synchronous reset on gated flops needs the clock to run. Force the enable on during reset or use an asynchronous reset.
Rule of thumb: if the synthesis report shows zero clock gates for a block you expected to gate, look at the enable.
Enable Quality Rules
The enable must be early, registered or short logic from registers, defined at reset, and synchronous to the clock source.
With a latch ICG the enable has a full cycle: 2.00 - 0.35 - 0.15 = 1.50 ns. A negative-edge AND gate gets 0.50 ns.
Wake-up must come from always-on logic, not from state that needs the stopped clock.
Rule of thumb: never derive the enable from the outputs of the gated registers.
Latch-Based Gating: Timing and Signoff
Check clock-gating setup and hold on the enable and test-enable pins, minimum pulse width, and gated-clock skew against the ungated flops.
Every gated clock comes from a library ICG with a connected test enable. Gated flops use an asynchronous reset or a running clock.
Simulate wake-up after a long idle period and compare the first outputs.
Rule of thumb: do not false-path gated and ungated data merely because a gate exists.
Mini project: close timing on an 8-tap FIR filter
Practice question: Low-power RTL design with clock gating
Practice question: ICG cell usage in RTL
Practice question: A safe clock gate with a latch-based enable
Code lab: Clock-gate control FSM
Interview: run a mock interview on this topic