Check | Where | Requirement |
|---|---|---|
Clock gating setup | Enable pin of the ICG (or the AND gate) | Enable stable before the active edge of the clock at the gate |
Clock gating hold | Enable pin | A latchless AND gate needs enable stable throughout the high phase. A latch ICG instead has library-characterised enable hold around the latch-closing (rising) edge; the latch does not eliminate this check |
Pulse width | Gated clock net | Minimum high/low width preserved |
Gated-clock skew | Leaf flops below the gate | Balanced against the ungated flops by CTS |
Latch time borrowing | ICG internal latch | Library-characterised; STA models it as a cell timing arc |
# STA infers gating checks on library ICG cells. Many tools also infer them
# on simple AND/OR gates where a clock meets a data signal, often with zero
# margin. Set the margin your methodology requires (check your tool's
# documentation), and confirm the check appears in the timing report:
set_clock_gating_check -setup 0.10 -hold 0.05 [get_cells u_gate]The gating setup check exists because an enable that misses the closing edge controls the wrong clock pulse. The simulation below drives two ideal ICGs on the same clock. Both enables are meant to let the edge at 15 ns through; one settles while clk is low, the other 1 ns after the edge.
The clock period is 10 ns and each slot is a quarter of it: two slots while clk is high, two while it is low. Each slot shows the values 0.62 ns after it starts.
On time: en_ok rises in slot 3, while clk is low and the latch is open. g_ok pulses on the next edge (slots 4 and 5), as intended.
Too late: en_late rises in slot 5, after the edge in slot 4 has closed the latch. g_late misses that pulse.
Wrong pulse: the latch captures the late 1 when clk falls, so g_late pulses in slots 8 and 9, on the edge both enables meant to turn off. The block runs one cycle late.
In silicon an enable that changes close to the closing edge can also violate the cell's setup or hold aperture and give a short or glitching pulse, not just a clean one-cycle slip. STA reports a late enable as a clock gating setup violation.
For a low-transparent latch ICG, check both enable setup and hold against the library's closing-edge arcs. A short enable path arriving 0.02 ns after that edge violates a +0.05 ns hold requirement by 0.03 ns even if setup passes. Actual arc values, including potentially negative hold values, come from the selected cell and corner; an ideal RTL latch cannot validate them.
Every gated clock is generated by a library ICG cell, not by logic.
Every ICG has a test enable connected to the scan network.
The enable and test-enable paths pass every applicable library setup and hold check in all signoff views, with margin; inspect both maximum- and minimum-delay paths.
The gated and ungated clocks are balanced by CTS (insertion delay and skew reports).
Gated flops use an asynchronous reset or the clock runs during reset.
Simulation covers wake-up: enable rises after a long idle period, and the first cycle is correct.
Power analysis shows the expected toggle reduction (gated clocks toggle only when enabled).
Time gated/ungated data paths as related clocks with the correct source/generated relationship and propagated skew; do not false-path them merely because a gate exists.
A wake-up test is easy to forget. Hold the block idle for hundreds of cycles, raise the enable, and compare the first outputs against a reference.
The safe-style checker explicitly holds en=te=0 for 300 cycles while changing d, checks zero gated edges and retained 0x3c, then requires 0xa5 on the first enabled edge and a hold on the following idle edge. Independent references also check test-enable loads and reset while stopped. Random traffic alone would not cover the long-idle scenario.
No. The closed latch isolates high-phase changes only after its closing-edge setup/hold requirements are met. Check the library arcs; a latchless AND gate additionally requires the enable to remain stable throughout the high phase.
The wake-up scenario comes from the safe-style bench, run with Icarus Verilog 13.0 (2026-10-16), which prints PASS. Ideal RTL cannot validate library hold arcs or physical signoff.