Rule | Why | How to follow it |
|---|---|---|
Early | The ICG latch closes at the rising edge; the enable must settle before that | Compute it in the previous cycle if possible |
Registered (or short logic from registers) | A long combinational enable path can make the gating check critical | Register the enable only if the interface allows the extra wake-up latency |
Glitch-free where it matters | The ideal latch tracks during low and blocks high-phase changes; hardware requires stability around its closing-edge aperture | Avoid asynchronous controls and meet library enable/test-enable setup and hold checks |
Defined at reset | An unknown enable makes simulated clock behavior unknown; hardware behavior is not guaranteed | Reset the enable flop or use an approved reset/test override; a known asserted override must dominate unknown controls |
Synchronous to the gated clock's source | An enable from another clock domain is a CDC crossing | Synchronise first; never use an unsynchronised enable |
With a low-transparent latch ICG, an enable launched at a rising edge can target the next rising closing edge. This illustrative budget assumes a common 2.00 ns period and zero skew/uncertainty; actual launch/gate clock latencies and margins must be included in STA. It does not waive the minimum-delay hold check at the current closing edge.
Read the bar from the launching edge on the left to the closing edge on the right. The shaded band is where the latch is open.
The enable leaves its flop 0.35 ns after edge 0 and then has 1.50 ns of logic.
It must be settled 0.15 ns before 2.00 ns, when clk rises and the latch closes. That edge is also the gclk edge the enable controls.
The enable may arrive while clk is still high, before the shaded band: the closed latch simply waits for the low phase. That is why the latch ICG gives the enable a full cycle.
Item | Value |
|---|---|
Clock period | 2.00 ns |
Enable flop clock-to-Q | 0.35 ns |
ICG setup to the rising edge | 0.15 ns |
Time left for enable logic | 2.00 − 0.35 − 0.15 = 1.50 ns |
A plain AND-based gate with the enable launched from a negative-edge flop gets only half a cycle: (T/2) − t_cq − t_setup = 1.00 − 0.35 − 0.15 = 0.50 ns. This is one reason to prefer the latch ICG: it gives the enable a full cycle.
Wake-up must originate in always-on, ungated logic or another source that can change while the block is stopped. A gated-domain state machine cannot wake itself if its only progress requires the stopped clock. Reset/test overrides need their own timing and release contract; neither is exempt from applicable ICG checks. Review and test the first accepted operation at the allowed wake-up latency.
1.25 − 0.30 − 0.12 = 0.83 ns.