Here α counts 0-to-1 charging events per cycle, C is switched capacitance, V is supply voltage, and f is clock frequency. An ungated clock has one charging event per cycle, so α=1. If activity instead counts both transitions, use P = (α_transitions/2) C V² f; then the clock has α_transitions=2. State the convention to avoid a factor-of-two error.
Quantity | Value |
|---|---|
Flip-flops in the block | 1,000 |
Clock-pin capacitance per flop (illustrative) | 2 fF |
Total leaf capacitance C | 1,000 × 2 fF = 2 pF |
Supply V | 0.9 V |
Frequency f | 500 MHz |
Clock power (ungated) | 2 pF × 0.81 V² × 500 MHz = 0.81 mW |
Assume illustratively that the block is active 18 % of cycles. A gate removes its leaf-clock charging events for the other 82 %. This is a budgeting assumption, not a measured activity.
Where the gate sits | Saves | Cost |
|---|---|---|
At each flop (one ICG per flop) | Only that flop's clock pin | One ICG per flop: overhead usually exceeds the saving |
At a group of 8 to 64 flops (typical ICG) | Their clock pins and the buffers below the gate | One ICG per group |
High in the tree (a whole block) | A large share of the clock tree | Few gates; must tolerate wake-up latency |
The example counts only leaf capacitance. Buffers below a gate may add gross savings; buffers above it still toggle. Net saving = avoided leaf and downstream-tree power minus ICG, enable-logic and added CTS/buffering overhead. Net savings can be smaller than the 0.66 mW leaf estimate, or even negative. Confirm them with implementation-aware power analysis and representative activity.
ICG power and area are one reason groups share a gate. Internal cell power, leakage and data-path activity are outside this simple capacitance estimate.
About 5 % of 0.81 mW = 0.04 mW, plus the small constant overhead of the ICG and its enable logic.
The 18 % activity and the 2 fF clock-pin capacitance are budgeting assumptions, not measured activity. The estimate counts leaf capacitance only.