Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
    • Reset Architecture
    • Metastability and Synchronisation
    • Asynchronous FIFO
      • Why an Async FIFO Is the Standard
      • Pointers and Gray Conversion
      • Full, Empty and the Complete Design
      • Almost Full and Almost Empty
      • Reset and Initialisation
      • Verification and CDC Closure
      • Sizing a FIFO, End to End
    • CDC Protocols
    • Reset Domain Crossing
    • CDC Verification
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
Loading lesson

‹Reset & CDC
  1. Topics
  2. RTL Design
  3. Reset & CDC
  4. Asynchronous FIFO

Part 6 · Reset & CDC · Intermediate

Asynchronous FIFO

An async FIFO moves data streams between unrelated clocks using Gray-coded pointers.

  • 7topics
  • 7lessons

Topics in this section

  1. 1Why an Async FIFO Is the Standard1 lesson
  2. 2Pointers and Gray Conversion1 lesson
  3. 3Full, Empty and the Complete Design1 lesson
  4. 4Almost Full and Almost Empty1 lesson
  5. 5Reset and Initialisation1 lesson
  6. 6Verification and CDC Closure1 lesson
  7. 7Sizing a FIFO, End to End1 lesson
On this page

    An asynchronous FIFO moves a data stream between two unrelated clocks. Data rests in a small dual-port memory while Gray-coded pointers cross through two-flop synchronisers.

    Write and read domains with a shared memory and pointer synchronisers between them.
    Data goes through the memory; only the Gray-coded pointers pass through synchronisers, two flops each.

    Lessons in this topic

    7 lessons, about 42 min

    1. 1Why an Async FIFO Is the StandardYou can explain why an async FIFO is the standard stream crossing, state its latency and flag costs, and say why its depth needs a bound for the real workload.5 min
    2. 2Pointers and Gray ConversionYou can build AW + 1 bit pointers, convert them to Gray before the register, and write the full test as the top two Gray bits inverted with the rest equal.6 min
    3. 3Full, Empty and the Complete DesignYou can read the complete async FIFO, explain why stale remote pointers make the flags safe but pessimistic, and use a binary-pointer mutant to show a test is sensitive.7 min
    4. 4Almost Full and Almost EmptyYou can choose MARGIN from the producer's reaction budget and explain why an almost flag never replaces full or empty.4 min
    5. 5Reset and InitialisationYou can reset both sides of an async FIFO safely: state the reset values, the hold time, and what the producer and consumer must not do during reset.4 min
    6. 6Verification and CDC ClosureYou can list the CDC closure points for an async FIFO, state the pointer skew bound, and show a test is sensitive with a binary-pointer mutant.7 min
    7. 7Sizing a FIFO, End to EndYou can size an async FIFO from burst length, both clock rates, idle cycles and the pointer crossing latency, round it for Gray pointers, and say when no depth is enough.9 min

    Interview

    “Design an asynchronous FIFO” is a classic. Cover: memory, binary pointer with one extra bit, Gray pointers, 2FF synchronisers, full compare with the top two bits inverted, empty compare equal, conservative flags, reset of both sides.

    Check yourself Which pointer crosses into the write domain, and what is it used for there?

    The read pointer, Gray-coded and synchronised into the write domain. The write side compares it with its own next write pointer to decide whether the FIFO is full.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Why an Async FIFO Is the Standard

    • Data never crosses a synchroniser. It waits in memory until the pointers mark it valid.

    • Costs: 2 or 3 read-clock cycles before a word is visible, and full and empty flags that report a few entries early.

    • B × max(0, 1 − f_r / f_w) is a steady-rate burst estimate, not a worst-case depth rule.

    Rule of thumb: a FIFO absorbs bursts; it does not match rates, so the producer must still stall on wfull.

    Pointers and Gray Conversion

    • Equal pointers mean empty. Pointers that differ only in the top (lap) bit mean full.

    • In Gray code, full is the top two bits inverted and the rest equal. Flipping only the top Gray bit is wrong.

    • Compare the next write pointer with the synchronised read pointer, so wfull registers on the same edge as the last write.

    Rule of thumb: convert to Gray before the pointer register, so the crossing wire is a flop and cannot glitch.

    Full, Empty and the Complete Design

    • wfull and rempty are registered and computed from the next pointer value, so they are glitch-free and correct in the cycle the pointer changes.

    • A stale remote pointer may delay progress. It cannot cause an overwrite or a read of an unwritten word.

    • The read data is mem[rbin], a first-word fall-through read. A memory with a registered read needs an output register and one extra cycle.

    Rule of thumb: keep the binary-pointer mutant in the bench: the failure it produces is the proof that the test works.

    Almost Full and Almost Empty

    • MARGIN must be at least the post-threshold arrivals minus guaranteed reads. Count reads as zero unless they are guaranteed.

    • almost_empty is not empty and almost_full is not full. The writer must still obey wfull.

    • A larger margin costs throughput that depends on the workload. Measure it under the warning policy you chose.

    Reset and Initialisation

    • Reset each side with its own synchronised reset, both from the same source at the same time, so the pointers clear together.

    • Hold reset at least 3 cycles of the slower clock after the pointers reach 0. No write while wrst_n is low and no read while rrst_n is low.

    • After reset, wfull = 0 and rempty = 1.

    Rule of thumb: any reset event that touches one side must reset or drain the whole FIFO.

    Verification and CDC Closure

    • Bit-to-bit skew must be below the minimum interval between pointer changes. The source period sets it, not the destination period.

    • Data crosses through memory as a qualified held-data path. Bound the write-to-read-data delay below the pointer-visibility latency, or register the RAM output.

    • Three things make it safe: Gray pointers, two-flop synchronisers, and flags derived conservatively from stale pointers.

    Rule of thumb: a clean CDC report does not prove the skew bound; read the achieved skew on each pointer.

    Sizing a FIFO, End to End

    • Depth = backlog from the rates + reads lost while the reader starts + reads the writer has not yet seen, then round up to a power of two.

    • Turn crossing latency into time, then into words at the slower rate: up to 4 cycles of each receiving clock for this design.

    • With an unbounded burst and a writer faster than the reader during it, no depth is enough: stall the writer on full or bound the burst.

    Rule of thumb: size for the worst moment, not the average rate, and count every cycle a pointer spends crossing.

    Practise it

    • Mini project: a two-clock block with a handshake, an async FIFO and a hostile test

    • Practice question: Design an asynchronous FIFO with CDC handling

    • Practice question: High-throughput CDC with an asynchronous FIFO

    • Practice question: Gray code counter for a CDC-friendly FIFO pointer

    • Code lab: Build a Gray code counter

    • Code lab: Async FIFO with Gray pointers

    • Interview: run a mock interview on this topic

    PreviousNext: Why an Async FIFO Is the Standard

    Up next

    Up nextWhy an Async FIFO Is the Standard

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Reset Architecture
    • Metastability and Synchronisation
    • CDC Protocols