A synchroniser carries one slowly changing bit. Events and single words need fuller protocols; streams use the asynchronous FIFO.
5 lessons, about 23 min
The source must know when the destination has captured the data before it can change the data or drop the request. The acknowledge is an asynchronous signal from the source's point of view, so it needs a synchroniser like any other single-bit crossing.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Choose a Protocol by Traffic Shape
Fast and slow clocks swap roles. A pulse from a fast to a slow clock must be stretched or toggled.
A pulse from a slow to a fast clock is safe through a plain 2FF only if it is long enough to be sampled at least twice.
Write the crossing choice and its throughput next to the interface, for example one config write per about 9 source cycles.
4-Phase Request/Acknowledge
Only req and ack cross. The data is stable from before req rises until after ack rises.
Throughput is low by design: both crossings repeat for the return to zero. Use it for control and configuration, not streams.
Every data bit must arrive before the earliest capture, about 2 destination periods after launch. A slow control path only adds budget.
Rule of thumb: never skip the return-to-zero half of the handshake.
Pulse Synchronisers and Event Toggles
Only the toggle level crosses. The XOR of q2 and q2_prev makes a one-destination-period pulse on every flip.
Keep pulse starts at least two destination periods apart. Closer flips can merge and a pulse is lost.
If each event must be conserved, use an acknowledged transfer, a sized counter crossed in Gray code, or a FIFO.
Rule of thumb: if the source can pulse faster than the destination can see, no structure helps; rate-limit the source.
Mux Recirculation for Multi-Bit Capture
Two inequalities must hold: data arrives before the earliest capture (about Ts + 2 × Td), and the next change comes after the latest capture (about Ts + 3 × Td).
The protocol does not enforce the hold time. A slower destination clock, for example from a power mode, can break it.
The source may not load again until ready returns, after the hold counter expires.
Rule of thumb: when the clock ratio is not fixed, use the 4-phase handshake.
CDC Handshake Checklist
Define the safe state (req and ack low) and reset both sides together. Add a timeout if a clock can be gated or a domain powered down.
Constraints are crossing-specific. A broad clock group can override a datapath-only max-delay exception, so audit the implemented reports.
Show a crossing is safe in three layers: approved structures, tests with a metastability model, and a CDC tool that classifies every crossing.
Rule of thumb: put each crossing in a named wrapper and keep the checklist next to it.
Mini project: a two-clock block with a handshake, an async FIFO and a hostile test
Practice question: A unified CDC strategy: handshake, FIFO and synchronisers
Practice question: Missing pulse in a CDC because the pulse is too narrow
Practice question: Multi-bit bus CDC with a request/acknowledge handshake
Code lab: CDC handshake
Code lab: CDC pulse stretch
Interview: run a mock interview on this topic