Resets put every domain in a known state and release each domain on its own clock. The rule is assert asynchronously and release synchronously, one synchroniser per domain in a planned order.
5 lessons, about 27 min
Releasing. With an asynchronous-assert design the reset takes effect without a clock; the release is passed through flops so that it happens right after a clock edge.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Reset Is a System Contract
After reset every flop that matters has a known value. Reset asserts without a clock, and releases only when each domain's clock is stable.
Reset only control state, valid bits and FSM state. Datapath registers that are written before use need none, and fewer reset flops means a smaller tree.
Never mix styles on one flop by accident: a synchronous reset in a gated-clock domain does nothing while the clock is off.
Rule of thumb: reset what must be known at start-up, and nothing else.
Async Assert, Sync Deassert
Recovery and removal are the setup and hold of reset release. A release at a random instant can violate either one.
Assertion needs no clock. Release takes two edges of the domain's own clock (STAGES must be 2 or more), so two domains release at different times.
Only the synchroniser sees the raw arst_n. Every other sink uses the domain's qualified reset.
Rule of thumb: assert asynchronously, release synchronously.
Reset Tree Planning
One synchroniser per clock domain, in that domain's clock. Never share one between clocks.
Distribute one settled reset per domain through a buffered tree. Do not synchronise the raw reset twice for interacting logic.
Name the contract: rst_n means already synchronised to this module's clock; a raw asynchronous reset is arst_n and stops at the synchroniser.
Rule of thumb: releasing two domains on the same cycle of their own clocks is not releasing them at the same time.
Reset Sequencing and POR Controller
The sequencer outputs are registered release requests, not local reset completion. With HOLD = 8 and GAP = 4 they rise at lock + 9, +13 and +17.
For a true A-before-B dependency, A raises a readiness level after reset and initialisation. It is synchronised back, and B's request waits for it.
A synchronous !pll_lock branch reacts only when the reference clock ticks. Route clock faults through the asynchronous reset path.
Rule of thumb: an ordered request is not an ordered release; wait for the acknowledgement.
What a Reset Costs
Reset what decides behaviour: FSM state, valid bits, counters and pointers that gate outputs, software-visible registers.
Data written before it is read, and qualified by a reset valid bit, needs no reset. Its x in simulation is real but unread.
A synchronous reset still loads the reset net: it moves from reset pins to a gate in every D path. Only removing resets shrinks the tree.
Rule of thumb: reset what decides; let a reset valid bit guard what carries.
Mini project: a two-clock block with a handshake, an async FIFO and a hostile test
Practice question: Reset strategies in RTL: synchronous, asynchronous and gated
Practice question: Why reset matters in FSMs and how it is handled
Practice question: Debugging metastability from asynchronous reset deassertion
Code lab: Build a reset synchroniser
Code lab: Build a pipeline register stage
Interview: run a mock interview on this topic