Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
    • Reset Architecture
    • Metastability and Synchronisation
    • Asynchronous FIFO
    • CDC Protocols
      • Choose a Protocol by Traffic Shape
      • 4-Phase Request/Acknowledge
      • Pulse Synchronisers and Event Toggles
      • Mux Recirculation for Multi-Bit Capture
      • CDC Handshake Checklist
    • Reset Domain Crossing
    • CDC Verification
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
Loading lesson

‹CDC Protocols
  1. Topics
  2. RTL Design
  3. Reset & CDC
  4. CDC Protocols
  5. Choose a Protocol by Traffic Shape

Part 6 · Reset & CDC · Intermediate

Choose a Protocol by Traffic Shape

Match each traffic shape to its crossing structure, throughput and cost.

On this page

    Why this matters

    A 5 ns pulse sent to a 20 ns destination clock can vanish in a plain two-flop synchroniser. The right crossing depends on the traffic shape, and the wrong choice shows up as lost events or corrupted words in the field.

    After this lesson you can: pick a crossing structure from the traffic shape (level, pulse, held word, stream) and state its throughput in destination periods.

    Traffic shapes

    Five traffic shapes cover most crossings. The table names the structure for each.

    What crosses

    Example

    Protocol

    Throughput

    Notes

    A slow level (a status bit, an enable)

    pll_locked, dma_enable

    2FF synchroniser

    n/a

    Must hold for more than 1 destination period plus setup/hold (1.5 to 2+ periods in practice)

    A single event (a one-cycle pulse)

    Interrupt request, start command

    Toggle with a justified spacing contract, or acknowledged event

    Open-loop spacing depends on clocks and resolution assumptions

    Don't use a plain 2FF: the pulse can be missed; use acknowledgement/counting/FIFO when every event must be conserved

    A word (config, command, status)

    16-bit register value

    4-phase handshake or load pulse with held data

    1 word per round trip (about 9 source cycles per word in the lesson's testbench; depends on the two clock ratios)

    Data stable between request and ack

    A stream

    Samples, packets, bytes

    Asynchronous FIFO

    Up to 1 word per slower-clock cycle

    Depth sized for the burst

    A counter or pointer

    FIFO pointer, timestamp

    Gray code + 2FF

    1 per sample

    Single-step changes only

    Choosing a structure

    The flow chart applies the same choice as a decision tree. Reason every step in destination-clock periods.

    Flow chart selecting a CDC structure from the traffic shape.
    A decision flow for choosing a crossing structure.

    Tip

    Write the crossing choice and its throughput next to the interface in the design document. “Config registers: handshake, one write per ~9 source cycles” is a requirement that shows up in software performance.

    Common mistakes

    Common pitfall

    Fast and slow clocks swap roles. A pulse from a fast clock to a slow clock must be stretched; a pulse from a slow clock to a fast clock is safe through a plain 2FF only if it is long enough to be sampled at least twice. Always reason in destination-clock periods.

    Check yourself An interrupt pulse lasts one 5 ns cycle in a 200 MHz domain and goes to a 50 MHz domain. Which structure?

    A toggle (pulse) synchroniser: the pulse (5 ns) is far shorter than the destination period (20 ns), so a plain 2FF could miss it. The toggle turns it into a level change that persists.

    Remember

    • Fast and slow clocks swap roles. A pulse from a fast to a slow clock must be stretched or toggled.

    • A pulse from a slow to a fast clock is safe through a plain 2FF only if it is long enough to be sampled at least twice.

    • Write the crossing choice and its throughput next to the interface, for example one config write per about 9 source cycles.

    Keep going

    • Practice: A unified CDC strategy: handshake, FIFO and synchronisers

    • Practice: Missing pulse in a CDC because the pulse is too narrow

    • Interview: run a mock interview on this topic

    Related topics

    • 4-phase handshake

    Previous

    172 / 350

    Next: 4-Phase Request/Acknowledge

    Up next

    Up next4-Phase Request/Acknowledge

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Pulse Synchronisers and Event Toggles
    • Mux Recirculation for Multi-Bit Capture
    • CDC Handshake Checklist