An async FIFO has state in both domains: the write pointer and wfull in the write domain, the read pointer and rempty in the read domain. After a reset both pointers must return to the same value (zero), otherwise the FIFO's idea of its occupancy is wrong forever.
Reset scenario | Result | Rule |
|---|---|---|
Both sides reset together, released in any order after both are cleared | Correct: empty, not full | Hold both resets at least until each side has seen a few clock edges |
Only the write side is reset | The read pointer still has its old value: occupancy is garbage (negative or full) | Never reset one side of a running FIFO |
Only the read side is reset | Same problem | Same |
Release of one side while the other is still in reset | The released side sees the other side's pointer (zero) and behaves correctly | Allowed, provided the resets are synchronised in their own domains |
Reset each side with its own synchronised reset (async assert, sync release; see reset architecture).
Assert both resets from the same source at the same time, so the pointers clear together.
Hold reset long enough for the pointer synchronisers to flush: at least 3 cycles of the slower clock after the pointers reach 0.
The producer must not write while wrst_n is low, and the consumer must not read while rrst_n is low (the testbench gates winc and rinc with the reset).
After reset, wfull = 0 and rempty = 1.
Read the lanes from left to right in cycles of the slower clock.
Both resets fall at the same moment from the same source, so both pointers are 0 together.
The resets stay low for at least 3 slower-clock cycles, so each synchroniser holds 0 before either side runs. The testbench holds them for 6.
Each side releases on its own clock, so the two releases are not at the same instant. That is allowed: the released side sees the other pointer at 0.
winc and rinc stay low until their own side is out of reset.
The simulation-model synchronisers of the previous lessons have no reset of their own. The testbench therefore holds both resets for six periods of the slower clock before releasing them.
In the real two-flop chain (SKEW = 0), the flops take the same reset as their domain.
wfull and rempty?wfull = 0 (nothing written) and rempty = 1 (nothing to read). The design's reset values reflect that.