Timing closure is iterative. Each violation is classified, fixed with the smallest robust change, and re-verified.
Path class | Signature in the report | Typical fix |
|---|---|---|
Logic-depth dominated | Many levels; cell delay dominates | Gate ECO first; pipeline cut if structural |
Route-dominated long net | One net dominates the delay | Repeater buffers |
High-fanout control | One driver with many endpoints | Clone the driver; buffer tree |
Constraint issue | Async or multicycle paths flagged | Fix the constraint, not the logic |
4 lessons, about 15 min
The ECO may have shortened minimum data delay or changed clock skew. Inspect the before/after paths: adding data delay normally helps hold, not setup. Re-run STA for setup and hold across all required views and confirm no new damage.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
The timing-closure loop in practice
Setup violations need less logic or wire delay, or added latency; hold violations need more minimum delay.
Slack is required minus arrival at the capture edge; negative setup slack means data arrives too late.
Classify with aggregate delays, slew and loads, not with the cell count.
ECO levers: sizing and buffering
Most late fixes are gate level: swap cells, add buffers or repeaters, clone drivers; the function is unchanged.
Hold ECOs add minimum delay and spend setup margin; advancing capture helps hold at the cost of setup.
Useful skew needs flow support and re-verification in every required view.
Rule of thumb: sign off setup and hold after every ECO.
When an RTL change is the right call
Escalate to RTL when local or shared gate repairs cannot robustly meet the budget.
The cut costs one cycle of latency on that path; the consumer must expect data one cycle later.
Delay the select and valid with the data; a steady select in simulation hides the mix-up.
Senior closure checklist
Scope every exception to named paths or clock groups, and pair every multicycle setup with its hold.
Every ECO re-verifies setup and hold across all required PVT, RC and mode views.
Closure evidence: clean timing checks, reviewed exceptions, and green regression after the final ECO.
Rule of thumb: validate the constraints before touching the logic.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Pipelined arbiter for timing closure
Interview: run a mock interview on this topic