Validate constraints before fixing logic. False-path and multicycle mistakes mimic real violations.
# not-run: SDC is not executable here
# Exceptions name a design reason, never a slack number.
# Example topology: scan_clk and func_clk are alternative waveforms on
# the SAME clock input/tree; only one exists in a given analysis mode.
# Review this physical exclusivity with DFT; it is not a CDC exception.
set_clock_groups -physically_exclusive -group [get_clocks scan_clk] -group [get_clocks func_clk]
# Reason: src_reg is held stable for two cycles and dst_reg samples every second cycle (enable-gated, checked by assertion).
# Setup and hold are always paired: relaxing setup to 2 cycles needs hold restored to 1.
set_multicycle_path 2 -setup -from [get_cells src_reg*] -to [get_cells dst_reg*]
set_multicycle_path 1 -hold -from [get_cells src_reg*] -to [get_cells dst_reg*]Read the clock edges as numbers 0 to 3. The arrows start at the launch edge.
Setup: with -setup 2 the data has two periods, edge 0 to edge 2.
Default hold: the tool checks hold one edge before the setup edge, edge 1. That demands the data stay old for a full cycle, which this path never needs.
-hold 1: moves the hold check back to edge 0, the normal same-edge check.
A wrong exception hides real paths from STA, and no logic change repairs a constraint problem. Scope every exception to the named paths or clock groups, pair every multicycle setup with its hold, and review each one with the designer who owns the path.
The clock-group example applies only to the stated shared-source/tree topology. Distinct clocks that coexist but are selected by a mux may need logically exclusive generated clocks on the shared downstream tree, without cutting valid paths between their upstream domains. Unknown relative phase calls for asynchronous groups and CDC handling, not an exclusivity claim. Prefer separate mission, shift and capture views with their actual clocks and mode controls; test capture can require relationships absent during shift.
No. Establish the clock relationship and actual interaction paths first. Scope exclusivity to the appropriate generated clocks/shared tree, or use mode-specific analysis; a broad group can hide real upstream transfers.
Track setup and hold together. Fixes trade one problem for the other, so every ECO re-verifies both.
No. Read the reported check type, launch/capture edges, data delay and clock skew. For a hold failure, consider minimum data delay or clock-path correction; for setup, reduce maximum delay or fix the relevant clock/constraint problem. Recheck both checks across all required views.
Prefer the smallest ECO that stays robust across PVT corners. A fix that holds at one corner and fails at another is not closed.
A shared cause across many endpoints calls for a shared diagnosis. Physical cloning, a buffer tree or constraint correction can still be the right gate-level fix. Escalate to RTL when reports show those options cannot robustly satisfy the budget and the architecture permits the required change.
Inspect load, slew, placement and shared branches. Physical driver cloning or a buffer tree may solve it without RTL changes. Choose RTL restructuring only when report-based comparison justifies it, including functional and latency costs.
A two-stage pipeline with valid tracking, proving data and valid stay aligned.
`timescale 1ns/1ps
module align_pipe (
input logic clk, rst_n,
input logic [7:0] d,
input logic v,
output logic [7:0] q,
output logic vout
);
logic [7:0] d1 = 8'h00, d2 = 8'h00;
logic v1 = 1'b0, v2 = 1'b0;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
d1 <= 8'h00; d2 <= 8'h00; v1 <= 1'b0; v2 <= 1'b0;
end else begin
d1 <= d; v1 <= v; d2 <= d1; v2 <= v1;
end
end
assign q = d2;
assign vout = v2;
endmodule