Gate level first

Most late-stage fixes happen at gate level first. They are localized and less disruptive than RTL changes.

A gate ECO swaps cells or adds buffers without touching RTL. Function is unchanged, so the existing regression stays valid.

Setup levers

Setup ECOs cut maximum delay along the complete failing path. An arc contributes regardless of its distance from capture. Rank candidates by cell/net delay sensitivity, input slew, output load and shared fanout; an early driver can dominate several later delays. Re-evaluate setup and hold on all affected branches after each change.

Hold levers

Hold ECOs add minimum delay on paths that are too fast. They spend setup margin, so each one re-verifies setup too.

For skew defined as capture arrival minus launch arrival, advancing capture helps hold at the cost of setup; delaying capture helps setup at the cost of hold. Clock changes affect other paths too, so useful skew needs flow support and re-verification across every required view.

Read each capture row against the dashed launch edges. The left edge is the hold check; the right edge is the setup check one period later.

• Advanced capture: the setup edge comes sooner, so the data has less time; the hold edge comes sooner, so new data is less likely to overrun it.

• Delayed capture: the reverse. Setup gains time, hold loses margin.

• Both edges move together, which is why a skew ECO always re-checks the other check on every affected path.

Common mistakes

Testbench

The repeated reductions below are a functional illustration; a checker enumerates all 256 binary inputs. Synthesis may merge every identical term. Implemented cloning requires the flow's synthesis/physical cloning command or reviewed preservation controls and placement. Inspect distinct mapped drivers, fanout per driver and routed timing before claiming load reduction or a timing gain.

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`timescale 1ns/1ps
module fanout_src (
  input  logic [7:0] d,
  output logic       y0, y1, y2, y3
);
  logic shared;
  assign shared = &d;                   // one term driving four loads
  assign y0 = shared;
  assign y1 = shared;
  assign y2 = shared;
  assign y3 = shared;
endmodule

module fanout_clone (
  input  logic [7:0] d,
  output logic       y0, y1, y2, y3
);
  assign y0 = &d;                       // repeated expression; physical cloning is not implied
  assign y1 = &d;
  assign y2 = &d;
  assign y3 = &d;
endmodule

module tb_fanout;
  initial begin
    #100000;
    $fatal(1, "FAIL: bounded bench watchdog expired");
  end
  logic [7:0] d = 0;
  logic y0s, y1s, y2s, y3s, y0c, y1c, y2c, y3c;
  logic exp;
  int errors = 0;
  fanout_src s (.d(d), .y0(y0s), .y1(y1s), .y2(y2s), .y3(y3s));
  fanout_clone k (.d(d), .y0(y0c), .y1(y1c), .y2(y2c), .y3(y3c));
  initial begin
    for (int vv = 0; vv < 256; vv++) begin
      d = vv[7:0]; #1;
      exp = &d;
      if (y0s !== exp || y1s !== exp || y2s !== exp || y3s !== exp) errors++;
      if (y0c !== exp || y1c !== exp || y2c !== exp || y3c !== exp) errors++;
    end
    if (errors == 0) $display("PASS: shared and cloned drivers agree on all 256 input values");
    else $fatal(1, "FAIL: %0d errors", errors);
    $finish;
  end
endmodule

Related topics

• The timing-closure loop in practice

• When an RTL change is the right call