The capstone is a configurable streaming peripheral. Software programs it through a control bus; input and output data use valid/ready streams; optional processing runs in a second clock domain; FIFOs absorb backpressure; errors produce sticky status and interrupts.
8 lessons, about 37 min
A filled reference configuration now anchors the stages: CP-1 is a one-input/one-output Q1.15 gain transform, not a frame accumulator. Keep this baseline reproducible before adding APB, selectable arithmetic or a framed MAC. The specification, traces and checker sketch below are supplied teaching artifacts; the complete peripheral, drivers, integration harness and measured signoff reports remain learner deliverables.
It requires consistent contracts and evidence across software, protocol, FIFO, CDC, arithmetic, verification, timing, low-power/DFT, and signoff boundaries.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Stage 1: Specification
Freeze clock domains, buffer policy, latency and numeric format before stage 2.
Each later artefact cites a requirement id, so a changed decision shows its cost.
The numeric reference is written down: round to nearest even, then clamp to 16 bits.
Rule of thumb: if a decision is not in the spec with an id, nobody can say what to verify.
Stage 2: CSR and Control
A command is an event: the CSR turns one accepted write into one internal pulse.
The response reports acceptance, not completion. Status and the interrupt report completion later.
A configuration snapshot is taken at START; a write while busy is rejected.
Rule of thumb: the bus adapter never reaches into datapath state; it hands over pulses, a snapshot and status events.
Stage 3: Buffered Streams
Payload, last, keep, tag and error flags travel together in one entry.
A transfer happens only on the edge where valid and ready are both high; counters count only those.
Graceful abort finishes the open packet, blocks new ones and drains accepted work.
Rule of thumb: never update last or a tag from request levels; it must ride with its data.
Stage 4: CDC and Reset
Streams cross through asynchronous FIFOs; start, config and done records cross by acknowledged handshake.
A one-sided reset closes admission, flushes both FIFO ends and starts a new recovery epoch.
Verify several clock ratios, phases and one-sided resets, not one lucky ratio.
Rule of thumb: hold a snapshot stable and cross it with a handshake; never cross a multi-bit value bit by bit.
Stage 5: Arithmetic and Reliability
A correctable error is fixed before use and sets ce on that beat; an uncorrectable one sets ue and poison and forces the data to zero.
A poisoned beat is still delivered, so it counts as delivered, not discarded.
Parity detects but cannot correct, and SECDED assumes at most two bit errors.
Rule of thumb: the real decoder and reporting path must be exercised, so inject faults without changing the normal encoder.
Stage 6: Verification
The key is (recovery_epoch, operation, packet_tag, beat_index), never the tag alone.
Per epoch: accepted = delivered + explicitly discarded + in flight.
A testbench is credible when each named mutation fails for the intended reason.
Rule of thumb: do not reuse the implementation code as the reference, or both sides share the same bug.
Stage 7: Constraints and Implementation
Reports use the exact parameter set and clock modes tested in stage 6.
A manifest binds the design, parameters, constraints, libraries, tools and extraction scripts.
Audit unconstrained paths and missing generated clocks before reading WNS.
Rule of thumb: a clean report is only as good as the constraints behind it.
Stage 8: Signoff Review
Every claim points to a specification row, a test or assertion, an implementation report and an owner.
Every waiver has an owner, rationale, evidence, expiry and impact.
Conditional approval fits only when the remaining work is bounded, owned and cannot invalidate accepted evidence.
Rule of thumb: present the capstone as a release argument; code is one part of it.
Practice question: Design a memory-mapped register interface with read and write support
Practice question: Synchronous FIFO design that blocks on full and empty
Code lab: AXI stream handshake
Practice question: Debugging metastability from asynchronous reset deassertion
Code lab: CDC handshake
Interview: run a mock interview on this topic