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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub
    • Waveform Debug Hub
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
      • Stage 1: Specification
      • Stage 2: CSR and Control
      • Stage 3: Buffered Streams
      • Stage 4: CDC and Reset
      • Stage 5: Arithmetic and Reliability
      • Stage 6: Verification
      • Stage 7: Constraints and Implementation
      • Stage 8: Signoff Review
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
  • Glossary and Notation
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‹Capstone: Resilient Streaming Peripheral
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. Capstone: Resilient Streaming Peripheral
  5. Stage 3: Buffered Streams

Part 9 · Senior · Senior

Stage 3: Buffered Streams

Compose valid/ready stages and the input/output FIFOs (asynchronous in CP-1) while preserving packet data, metadata, ordering, and backpressure.

Why this matters

If last, a tag or an error flag sits in a side register, a stall can slide it off its data and the output frames the wrong beat. The failure appears only under backpressure.

After this lesson you can: store payload and packet metadata in the same FIFO entry, hold valid and data through a stall, and state what a graceful abort does with an open packet.

Store payload and packet metadata together so stalls and FIFO movement cannot separate last, byte enables, tags, or error flags from their data.

design.sv
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typedef struct packed {
  logic [31:0] data;
  logic [3:0]  keep;
  logic        last;
  logic [3:0]  tag;
  logic [1:0]  beat_index;
  logic [31:0] epoch;
  logic [31:0] operation;
  logic        ce;
  logic        ue;
  logic        poison;
} beat_t;

assign in_take  = s_valid_i && s_ready_o;
assign out_take = m_valid_o && m_ready_i;
  • Input ready derives from real storage availability.

  • Output valid and payload hold stable through stalls, including the accepting edge.

  • Counters update on accepted transfers only.

  • Graceful abort finishes the currently owned packet, blocks new packets, and drains accepted work; shared reset cancellation is a different operation.

  • Watermarks reflect reaction latency, not arbitrary percentages.

The input wrapper assigns tag=packet ordinal 0..15 and beat_index=0..3, plus current operation and recovery epoch. A tag is not reused within that operation; all old owners retire before another operation reuses it. These fields and ce/ue/poison travel in the same beat storage/pipeline. Output TUSER carries the owner/status fields; their absence in a narrower external interface requires an explicitly aligned status channel, not independent side registers.

Abort with a stalled output

IO edge

Input/command action

Output / ownership

C0

ABORT commits with no open input packet; new packet ready goes low

A=(epoch7,op3,tag0,index0) is already valid and stalled; every field remains unchanged

C1-C3

No new packet acceptance; B is already buffered

A remains offered, even if software clears status

C4

Receiver raises ready

A transfers once; B may replace it after the edge

C5

No new input

B, the final accepted beat with LAST=1, transfers once

C6+

Drain and DP counter snapshot acknowledge

Set ABORTED/IRQ, clear busy; no internal beat was discarded by graceful abort

Each slot shows the values just before edge C0 to C6, so it shows what that edge commits; m_data is x when nothing is offered.

  • C0: ABORT commits. s_ready is low from C1 on, so no new packet is accepted.

  • C0 to C3: m_valid stays high and m_data stays A while m_ready is low. The offer is never withdrawn.

  • C4: m_ready is high, so A transfers once and B moves to the head.

  • C5: B, which carries LAST=1, transfers once. At C6 nothing is offered and the drain is complete.

If ABORT arrives with an open input packet, input acceptance remains enabled only for its remaining beats through the real LAST, at most four total beats under CP-PKT. Do not accept the next packet, invent LAST on a previously offered beat, or withdraw VALID. All accepted packets drain in order, so the consumer sees complete framing. If the source fails to finish that packet or the receiver stalls forever, the watchdog reports a closed fault; ordinary stream semantics cannot guarantee abort completion without environment progress. Coordinated interface reset may cancel the offer only under a shared source/sink epoch contract. This follows the AXI-Stream offer/hold rule.

With the stream contract fixed, the design can move the processing pipeline to another clock without changing packet meaning. Both asynchronous FIFOs carry the complete beat_t, including last, keep, and tag.

Common pitfall

Never put last or a tag in a side register updated from request levels. It must travel in the same accepted transaction and storage entry as data.

Check yourself A stream beat stalls for five cycles. How many input counter increments occur?

One, on the edge where valid and ready are both high. Valid-high cycles are not transfers.

Remember

  • Payload, last, keep, tag and error flags travel together in one entry.

  • A transfer happens only on the edge where valid and ready are both high; counters count only those.

  • Graceful abort finishes the open packet, blocks new ones and drains accepted work.

Rule of thumb: never update last or a tag from request levels; it must ride with its data.

Keep going

  • Practice: Synchronous FIFO design that blocks on full and empty

  • Code lab: AXI stream handshake

  • Interview: run a mock interview on this topic

Related topics

  • Synchronous FIFO

  • Asynchronous FIFO

  • Valid/ready

  • Stage 4: CDC and reset

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See also

  • Stage 1: Specification
  • Stage 5: Arithmetic and Reliability
  • Stage 6: Verification
clkaborts_readym_validm_readym_dataabx
ABORT closes admission at C0 while A waits at a stalled output; A transfers once at C4 and B, the last accepted beat, at C5