Stage 1 writes every externally visible decision down with an id before any RTL exists. Later tests, assertions and reports cite those ids, so a changed FIFO policy or numeric format shows its verification and implementation cost.
Read the diagram top to bottom. The box labelled clk_io runs the control and stream sides, the box labelled clk_dp runs the transform, and everything that joins them is a clock-domain crossing.
CP-CTRL: the AXI-Lite master and the CSR/control FSM sit on clk_io.
CP-CLOCK: the supervisor stays on clk_io so it can contain faults while clk_dp is stopped or reset.
CP-BUF: both streams cross through 16-entry async FIFOs; the START/config and done/error records cross by acknowledged handshake, not FIFO.
CP-LAT: the datapath is two elastic register ranks, so data and metadata move together.
One line each. The full text, which is the contract, follows in the sub-tables below.
ID | In one line |
|---|---|
CP-CTRL | 32-bit AXI4-Lite control, one outstanding request per direction, SLVERR for anything unsupported |
CP-NUM | Q1.15 sample times Q1.15 COEFF, rounded once to nearest even, saturated to 16 bits |
CP-PKT | 1 to 16 packets of 1 to 4 beats per operation; TLAST closes each packet |
CP-CLOCK | clk_io 100 MHz for control, streams and supervisor; unrelated clk_dp 125 MHz for the transform |
CP-BUF | 16-entry async FIFOs in both directions, show-ahead, acceptance gated on real capacity |
CP-LAT | Two elastic ranks; at least 1 beat per clk_io sustained; empty-system latency target 24 clk_io periods |
CP-FAIL | Graceful abort finishes the open packet and drains; only shared reset may cancel, with accounting |
CP-REL | SECDED on the 32-bit payload, parity on metadata; UE poisons, corrupt metadata quarantines |
CP-PARAM | Width 32 and 15 fractional bits fixed; COEFF resets to 0x4000; unsupported configurations rejected |
CP-PROGRESS | Stated source/sink progress assumptions; 4096-cycle operation and 1024-cycle recovery watchdogs |
Start with the numbers. COEFF = 0x4000 is 16384, which is 0.5 in Q1.15. The product keeps 30 fractional bits, so dividing by 32768 brings it back to Q1.15.
Input code | COEFF code | Product (F=30) | Product / 32768 | Nearest even | After saturation |
|---|---|---|---|---|---|
+1 | 16384 | 16384 | 0.5 | 0 | 0 |
-3 | 16384 | -49152 | -1.5 | -2 | -2 |
-32768 | -32768 | 1073741824 | 32768 | 32768 | 32767 |
Read each row left to right. The first two rows are exact ties, so the tie rule decides the answer; the last row is the one product that does not fit in 16 bits.
Row 1: 0.5 lies halfway between 0 and 1; nearest even picks 0.
Row 2: -1.5 lies halfway between -2 and -1; nearest even picks -2.
Row 3: -1 times -1 is +1, which Q1.15 cannot hold, so +32768 clamps to +32767.
The numeric reference is integer product -> independent nearest-even division by 32768 -> clamp [-32768,32767]. Unclipped error relative to exact stored operands is at most half an output LSB (2^-16); clipping and input sampling error are separate. Reuse the canonical quantizer, not a second divergent rounding policy.
ID | Reference configuration / acceptance requirement |
|---|---|
CP-CTRL | 32-bit AXI4-Lite, byte addresses, one outstanding request per read/write direction; pair AW/W independently. Each internal committed CSR operation occurs once. Mapped accesses use OKAY; unsupported offsets, modes and busy configuration writes use SLVERR. APB is an extension, not another simultaneous control owner. |
CP-PKT | One operation accepts PACKETS=1..16 packets of 1..4 beats each. TLAST closes each packet. KEEP=1111 on nonlast beats; final KEEP may be 1111 or 0011. The low two bytes always contain a complete sample; upper input bytes are padding and ignored by arithmetic. Output KEEP/LAST are preserved; valid upper output bytes are sign extension. Malformed framing is a protocol fault requiring coordinated recovery, not a silently successful packet. |
CP-PARAM | Data width=32 and fractional bits=15 are fixed in CP-1; packet count 1..16; packet length 1..4; FIFO depths power-of-two >=2; COEFF reset=0x4000 (0.5). Reject unsupported configurations instead of silently changing byte stride or framing. Broader widths/modes are separately verified extensions. |
ID | Reference configuration / acceptance requirement |
|---|---|
CP-NUM | Each beat contains signed Q1.15 sample in data[15:0]. Multiply by signed 16-bit Q1.15 COEFF, retain signed 32-bit F=30 product, round once to nearest-even F=15, then saturate to 16 bits and sign-extend to 32. No accumulation or averaging. |
ID | Reference configuration / acceptance requirement |
|---|---|
CP-CLOCK | clk_io=100 MHz owns AXI-Lite, streams and an always-on recovery supervisor; unrelated clk_dp=125 MHz owns the transform. clk_io must keep running for fault containment. The implementation may gate/stop clk_dp only under the recovery contract. |
CP-BUF | Input/output async FIFOs default to 16 entries each, power-of-two depths >=2. Carry complete beats, use show-ahead adapters with persistent valid/ready offers, and gate acceptance on actual capacity. A registered-read resource needs prefetch/result storage; it is not a drop-in show-ahead FIFO. |
CP-LAT | Two elastic processing register ranks: no-stall DP acceptance at D0, result available after D1, downstream consumes at D2. Stalls hold data and metadata together. Target >=1 beat/clk_io sustained after fill when both streams permit; empty-system no-stall acceptance-to-output target <=24 clk_io periods, to be measured and justified rather than assumed. |
ID | Reference configuration / acceptance requirement |
|---|---|
CP-FAIL | Graceful abort blocks new packets but finishes an already open input packet, then drains every accepted beat. Shared interface reset may cancel in-flight work with explicit epoch/drop accounting. No ordinary VALID offer is withdrawn merely because abort arrived. |
CP-REL | Baseline FIFO payload protection is SECDED for 32 data bits plus separate parity over immutable owner/framing metadata. CE corrects payload before use; payload UE with trusted metadata produces zero data with poison/UE. Detected metadata corruption instead quarantines the operation for coordinated cancellation; never forward guessed framing. Freeze decoder convention and protection granularity before coding. |
CP-PROGRESS | Assume progressing clocks, a source that completes each legal packet within 8 eligible input edges, and a sink that accepts each output offer within 8 offered edges. Under those assumptions, use an illustrative 4096-clk_io-cycle operation watchdog; derive the bound from FIFO residence, CDC, service gaps and counter return. Recovery has a separate 1024-cycle watchdog; expiry stays faulted/closed and cannot retract a stalled output offer without shared reset. |
The ten requirements answer these seven questions. Use the table to check that a new design's spec has an answer for each row.
Contract | Required decisions |
|---|---|
Control | AXI-Lite or APB, register map, errors, software sequence |
Streams | Width, valid/ready, packet markers, backpressure |
Processing | Operation, fixed-point formats, rounding, saturation, latency |
Clocks/resets | Domains, relationships, release order, clock-loss behavior |
Buffers | Depths, output mode, almost thresholds, overflow policy |
Reliability | Parity/ECC scope, CE/UE reaction, injection |
Performance | Sustained throughput, max latency, outstanding/burst assumptions |
Requirement | Supplied anchor | Learner implementation / required evidence |
|---|---|---|
CP-NUM | Formats, tie/clip examples and canonical quantizer lesson | Bit-exact independent model, signed boundaries/ties/clips, aligned two-rank elastic pipeline; compile/simulate and archive verdict |
CP-FAIL | Stalled-output abort trace in stage 3 | Controller + adapters; mutation withdrawing VALID must fail stability, drain and ownership checks |
CP-CLOCK | Crossing inventory and stopped-clock recovery trace in stage 4 | Reset/CDC wrappers, per-bit timing/skew reports, recovery acknowledgements and epoch evidence |
CP-REL | Partial-final-beat CE/UE trace in stage 5 | Actual encoder/decoder, persistent corruption and repair tests, aligned error records and IRQ checks |
CP-LAT | Acceptance/visibility/consumer convention and target | No-stall and bounded-stall timestamp checks plus mapped timing/QoR; no measured result supplied here |
Stage 1 is frozen when every item below is written down and has an id.
Clock domains, frequencies and the owner of each interface (CP-CLOCK, CP-CTRL).
The numeric reference as integer steps, with the three worked codes above as tests (CP-NUM).
Packet framing limits and what happens to malformed framing (CP-PKT).
Buffer depths, show-ahead behaviour and the acceptance rule, including simultaneous push/pop at full and empty (CP-BUF).
The latency convention (accept at D0, visible after D1, consumed at D2) and the 24-period target (CP-LAT).
Abort and reset behaviour from an active operation, with drop accounting (CP-FAIL).
Protection scope, decoder convention and granularity (CP-REL).
Every parameter with its legal range and default; unsupported configurations rejected (CP-PARAM).
Progress assumptions and watchdog bounds (CP-PROGRESS).
Invariants for accepted inputs, produced outputs, ordering and conservation, and one traceability row from each requirement to its test, assertion or report.
The product is 49152; divided by 32768 it is 1.5, an exact tie between 1 and 2. Nearest even picks 2, which fits in 16 bits, so the output is 2.
The exact acceptance and boundary policy: what happens to simultaneous push/pop at full and empty, plus output latency and data-valid meaning.