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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub
    • Waveform Debug Hub
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
      • Stage 1: Specification
      • Stage 2: CSR and Control
      • Stage 3: Buffered Streams
      • Stage 4: CDC and Reset
      • Stage 5: Arithmetic and Reliability
      • Stage 6: Verification
      • Stage 7: Constraints and Implementation
      • Stage 8: Signoff Review
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
  • Glossary and Notation
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‹Capstone: Resilient Streaming Peripheral
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. Capstone: Resilient Streaming Peripheral
  5. Stage 7: Constraints and Implementation

Part 9 · Senior · Senior

Stage 7: Constraints and Implementation

Deliver clock/IO constraints, CDC intent, synthesis expectations, physical hooks, DFT readiness, and reproducible QoR.

Why this matters

A block-level timing report can be clean because generated clocks or IO delays are missing. Reading worst slack before auditing coverage gives a false pass.

After this lesson you can: list the implementation checks a streaming block needs, audit constraint coverage before reading slack, and bind reports to the design and tools that produced them.

Check

Expected artifact

Lint

Zero errors; reviewed warnings/waivers

CDC/RDC

Crossing report with approved structures, reset epochs and containment

SDC

Primary/generated clocks, IO delays, crossing-specific exceptions and effective bundled-data/Gray bounds; no broad group silently overrides required paths

Synthesis

Storage mapping (flop array, register file or macro, as CP-BUF chose), area and unconstrained-path report

STA

Setup/hold by mode/corner, interstage timing and clock-gating checks

Power

Clock gating/activity report and mode assumptions

DFT

Scan-ready lint, test clock/reset hooks, memory inventory

Physical

Hierarchy, floorplan pins, congestion/fanout review

The two clocks in SDC

CP-CLOCK gives two unrelated clocks. The fragment below declares them and bounds every path between them instead of cutting those paths.

Diagram
# not-run: SDC is not executable here
# CP-CLOCK: clk_io 100 MHz, clk_dp 125 MHz, no phase relationship
create_clock -name clk_io -period 10.000 [get_ports clk_io]
create_clock -name clk_dp -period 8.000  [get_ports clk_dp]

# Every crossing (Gray pointers, handshake req/ack, config bundle,
# response record) gets a datapath-only bound. 8.000 ns is the shorter
# period; derive the real bound from each FIFO and handshake design.
set_max_delay -datapath_only 8.000 -from [get_clocks clk_io] -to [get_clocks clk_dp]
set_max_delay -datapath_only 8.000 -from [get_clocks clk_dp] -to [get_clocks clk_io]

# Not used: set_clock_groups -asynchronous would also remove the bounds above.
# IO delays for the AXI-Lite and stream ports follow, per interface.

Read it as two declarations and two bounds. The bound keeps Gray-pointer bits and bundled data from arriving so late, or so skewed, that a synchroniser samples a mix of old and new values.

These reports use the exact parameter set and clock modes tested in stage 6. A manifest binds the elaborated design, parameter revisions, constraints, libraries, tools, and report extraction scripts so the signoff review can reproduce every headline result.

Common pitfall

A clean block-level STA report with missing generated clocks or IO delays is not clean timing. Audit coverage and unconstrained paths before reading WNS.

Check yourself What evidence confirms the FIFO storage mapped to the resource the specification chose (flop array, register file or two-port macro)?

The synthesis memory inference/mapping report, supported by area/cell counts and the expected storage instance in the netlist. Record the chosen resource in CP-BUF so the report has a target to match.

Remember

  • Reports use the exact parameter set and clock modes tested in stage 6.

  • A manifest binds the design, parameters, constraints, libraries, tools and extraction scripts.

  • Audit unconstrained paths and missing generated clocks before reading WNS.

Rule of thumb: a clean report is only as good as the constraints behind it.

Keep going

  • Interview: run a mock interview on this topic

Related topics

  • RTL implementation closure

  • DFT-ready RTL

  • Stage 8: Signoff review

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See also

  • Stage 1: Specification
  • Stage 2: CSR and Control
  • Stage 3: Buffered Streams