Physical awareness means writing RTL that places and routes well. Short routes close timing, spread logic avoids congestion, and clean boundaries match the floorplan.
4 lessons, about 15 min
Diagnose cell/net delay, slew, load, placement and constraints. Compare repeaters, physical driver cloning or route changes; consider a register boundary only when the interface latency budget permits it.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Why RTL structure affects place and route
Wide buses, uncontrolled cross-hierarchy fanout and late muxing are the three structures that hurt.
1024 loads at a fanout of 8 need 4 buffer levels; a replica per 256-flop cluster needs 3 and stays local.
Identical RTL registers can be merged by synthesis; use the flow's duplication or preservation controls.
Rule of thumb: locality is a hypothesis: compare mapped topology and routed QoR before and after.
Wire-length-aware micro-architecture
A slice adds latency, not meaning: delay the qualifier and the data together.
Throughput stays one transfer per cycle; latency grows by one cycle per stage.
From E0 launch to E2 output is two cycles, and a downstream flop consumes at E3.
Congestion-aware coding patterns
Mux and decode close to the data origin; merge only the group winners.
Two 4:1 muxes plus a 2:1 suggest local grouping, but synthesis can flatten them.
Judge the result by routed congestion and timing under identical flow settings.
Floorplan hooks and hierarchy contracts
Keep partition crossings registered; use the bypass only inside one block.
USE_SLICE changes latency and reset behaviour, so carry both in the integration contract.
Physical partitions and reset domains need not coincide; independent resets need boundary recovery handling.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Two-stage valid/ready pipeline: throughput versus latency
Interview: run a mock interview on this topic