Area | RTL owner supplies | Detailed owner/course |
|---|---|---|
MBIST | Memory inventory, wrapper ports, clocks/resets, repair/status path | DFT MBIST & LBIST |
JTAG/boundary scan | Pin mux ownership, TAP/reset connectivity, lifecycle policy | DFT Boundary Scan & JTAG |
Compression | X-source inventory, mask/control hooks, domain partition | DFT Compression & Diagnosis |
ATPG | Legal test modes, constants, black-box models | DFT ATPG & Patterns |
Physical | Clock/domain/hierarchy intent and test ports | DFT Physical Integration |
The final handoff maps both sensor SRAMs to memory built-in self-test (MBIST), assigns the external pins to the boundary-scan policy, and documents the analog-status clamp so automatic test pattern generation (ATPG) and compression do not inherit an uncontrolled unknown source.
Read the left side as memory test and the right side as logic test. Dashed arrows are status coming back.
Memory instance | Test mapping / resource-specific contract | Release artifact |
|---|---|---|
u_sensor/u_sample_sram | u_sample_mbist -> sample wrapper, 256x16; exclusive port ownership, documented read latency and write/read collision rules | Macro model revision, algorithm/clock limits, done/fail mapping to TAP status[0:1]; repair unsupported in this illustrative macro |
u_sensor/u_cfg_sram | u_cfg_mbist -> config wrapper, 64x32; separate bus test clock and port ownership; destructive test requires config reload | Own macro model/latency limits, done/fail mapping to TAP status[2:3]; repair unsupported here |
Handoff acceptance requires both named instances mapped exactly once, no unresolved memory wrappers, reviewed per-mode clocks/reset assumptions, chain-domain inventory, pin parking expectations and clamp/mask coverage exclusions. Analog clamp=0 intentionally removes that source from scan fault observation; it needs a separate analog test plan. MBIST completion does not authorize functional traffic until reset/configuration initialization and domain readiness finish. Macro fault coverage, insertion, ATPG patterns and physical test timing remain DFT-owned evidence, not inferred from this inventory.
Version the memory instance list and map every instance to MBIST/repair policy.
Review JTAG access against security lifecycle and production lock requirements.
Identify X sources before compression insertion; uncontrolled X values destroy observability.
Provide test-mode SDC assumptions and confirm they do not leak into functional modes.
Close DFT DRCs or attach owned, expiring waivers.
A single unknown can spread through the response compactor and mask many observable bits, reducing useful fault coverage.