Timing interviews test whether a fix starts from the report. Each lesson below is one realistic question with a complete model answer.
Check | Meaning | Arithmetic |
|---|---|---|
Setup slack | Data arrives early enough before the capture edge | slack = required − arrival; required = T + skew − setup − uncertainty |
Hold slack | Data stays stable long enough after the capture edge | slack = arrival − required; required = hold + uncertainty + skew |
Here skew means capture-clock arrival minus launch-clock arrival. Positive skew helps setup but hurts hold. These simplified equations omit separate early/late derates and clock reconvergence adjustments; use the signoff report for those terms.
4 lessons, about 19 min
Fix the setup violation first. Slowing the clock helps setup only. Hold is independent of the period, so it needs its own fix.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Reading a critical path report
Slack is required minus arrival; negative means the path misses.
Split arrival into clock-to-Q, logic and net delay before proposing a fix.
A frequency estimate T_min = T - s applies only to same-clock, single-cycle paths; re-run STA.
Rule of thumb: diagnose with the path and clock terms; slack alone only reports the score.
Fixing setup vs hold violations
Setup needs less maximum delay or more budget: less logic, a faster implementation or a pipeline cut.
Hold needs enough minimum delay or less harmful skew, and has no period term.
Order fixes setup first, then hold, and recheck both in every view.
Rule of thumb: a pipeline cut changes latency, so move the valid and handshake logic with the data.
False paths and multicycle paths you must justify
A false path needs a mode, a functional exclusion or a verified protocol contract; a multicycle path keeps a longer check.
Setup N moves capture to NT; hold N-1 restores the original hold edge at 0.
Do not cut a whole synchroniser; scope the exception to its first stage.
Rule of thumb: every exception carries a reason, evidence and a reviewer.
Corners, sign-off and clock-gating checks
Run setup and hold across every mandated process, voltage, temperature, RC and mode view.
Uncertainty covers jitter and margin; use derates or AOCV/POCV for path variation, and do not double count.
A gating enable needs setup and hold margin at the gating cell, in test and mission mode.
Rule of thumb: nominal-clean is not signoff; every required view must close.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Code lab: Timing exception path
Practice question: Integrated clock gating (ICG) cell usage in RTL
Interview: run a mock interview on this topic