Senior low-power questions test activity-first thinking. The strongest answers name the switching they remove, the boundary they protect, and the intent they leave to the tools.
4 lessons, about 20 min
Consider clock gating with an intent-driven enable and compare its savings with overhead. Use a characterized ICG or supported target clock-enable resource, including test control and gating timing. Rising-edge registration alone cannot make a raw AND gate safe.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Dynamic power first
Voltage and frequency are set above RTL. RTL owns the activity factor and, through structure, the capacitance.
Clock gating removes clock-tree activity. A data enable holds Q but leaves clock activity. Isolation stops switching in a cone.
Measure switching activity first, then gate. An enable should express design intent, such as idle or stall.
Rule of thumb: lead with the switching you remove, then name the mechanism.
Clock gating done safely
A low-transparent latch holds the enable while the clock is high, so the gated clock never has a runt pulse.
The ICG still has setup and hold requirements at latch closure, for both the enable and the test control.
Every gate needs a scan override, and one enable should serve a functional cluster, not a single flop.
Rule of thumb: never write clk & en in RTL; use the library ICG and let the backend insert it.
Crossing a powered-off domain
Clamp the off domain's outputs to the receiver's idle value, usually 0, before they reach live logic.
Shutdown: quiesce, save, isolate, power off. Wake: qualified power, restore, safe reset release, then release isolation.
Power-good alone does not make a domain safe. Restore and readiness belong to the current wake epoch.
Rule of thumb: isolation goes on before power goes off, and comes off only after the domain is ready.
The RTL and UPF split
RTL owns behaviour and exposes control: enables, idle signals, quiesce handshakes, save and restore triggers.
UPF defines the power structure built on those signals: domains, switches, isolation, retention.
The always-on controller owns the order of quiesce, isolate, switch, save and restore.
Rule of thumb: expose the signal in RTL and let UPF own the cell.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Low-power RTL design with clock gating
Practice question: A safe clock-gating cell with a latch-based enable
Practice question: Isolation cells and a boundary wrapper: clamp logic and power-good
Code lab: Isolation cell model
Interview: run a mock interview on this topic