The interviewer asks how to cut dynamic power at RTL, or what to do about a block that burns power while idle. It is really testing whether activity leads the answer.
Dynamic power follows P = α·C·V²·f. Voltage and frequency are set above RTL, so RTL owns the activity factor α and, through structure, the capacitance C.
At senior level, name the boundary whose switching is unnecessary. Clock gating suppresses downstream clock-tree and clock-pin activity plus gated state updates; a register data enable holds Q but may leave clock activity. Operand isolation suppresses changes from selected inputs into a combinational cone. Its other operands and controls can still switch. Rank alternatives using the same workload, capacitance and implementation overhead.
Lever | RTL move | When it pays |
|---|---|---|
Activity α | Gate clocks with intent-driven enables | Idle states, empty FIFOs, stalled pipelines |
Activity α | Hold operands steady at unused logic | ALU inputs, multiplier operands, idle datapaths |
Capacitance C | Narrower datapaths, less speculation | Over-wide buses, rarely used wide paths |
V and f | Expose the hooks, decide elsewhere | RTL provides enables and idle signals for DVFS policy |
Measure switching activity first, then gate. An enable should express design intent, such as an idle state or a stalled pipeline, not a local optimization.
When is clock gating better than operand isolation? It can save more when a large clocked cluster is idle. Isolation can save more when a costly combinational cone is driven by changing operands while its result is unused. Include gate/mux overhead and residual switching in both alternatives.
Does isolation help if the flops still toggle? It helps the combinational cone, not the flops. If the registers also sit idle, gate them as well.
Where does the hold signal come from? From the same intent as a clock-gate enable: decode idle, valid, or select signals one stage early so the hold is stable before the data moves.
Lowering VDD in the RTL. Supply is a platform decision, not a register-transfer one. RTL exposes idle signals; policy acts on them.
Gating the clock with `clk & en`. An AND on the clock glitches whenever the enable can change while the clock is high, and it gives the tools no gating check. The next lesson shows the latch-based cell that avoids this.
Holding inputs without a real idle condition. A mux without intent adds area and hides bugs. The hold must come from the control path.
Isolate unused operands and gate idle pipeline clocks when the protocol permits. Compare residual cone switching, clock load and control overhead; valid duty cycle alone does not rank them.
Explicitly hypothetical model: same 100-cycle workload, 75 idle | Clock energy units | Cone energy units | Overhead | Total |
|---|---|---|---|---|
Baseline | 100 | 200 | 0 | 300 |
Clock gating only; external operands still change | 25 | 200 | 5 | 230 |
Operand isolation only; modeled idle cone activity removed | 100 | 50 | 10 | 160 |
Both mechanisms | 25 | 50 | 15 | 90 |
Read each bar left to right: the accent part is clock energy, the light part is the combinational cone, the dark tip is the overhead the mechanism adds.
In this model the cone is the bigger cost (200 of 300), so isolation saves more than gating: 160 against 230.
Gating only shrinks the clock part; isolation only shrinks the cone part. Each adds its own overhead.
Both together reach 90, but only because the model assumes their savings do not overlap.
These additive energy units assume clock/cone costs of 1/2 per cycle and complete idle-cone suppression only for the modeled all-input isolation. They are not measured power or a prediction for the one-input mux below. If gating also holds the cone's driving registers, avoid double-counting that saving. Actual decisions need activity, mapped capacitance, voltage, frequency, glitches and leakage under identical workloads.
An operand clamp plus a functional sweep in both modes. It checks selection, not power savings.
`timescale 1ns/1ps
module op_iso #(
parameter int W = 8
) (
input logic [W-1:0] a_i,
input logic hold, // 1 while the consumer ignores this operand
output logic [W-1:0] a_o
);
assign a_o = hold ? '0 : a_i; // this operand stays zero; other inputs/control may switch
endmodule
Operand clamp bench Run with Icarus Verilog 13.0 (2026-10-16): prints PASS. It checks selection in both modes, not power savings or all downstream switching.
The energy table is a hypothetical model, not measured power: same 100-cycle workload, additive energy units, complete idle-cone suppression only for all-input isolation.