The question

The interviewer asks for a safe clock-gating pattern, or what is wrong with ANDing the clock with an enable. It is testing for the latch-based cell and the habits around it.

A direct clk & en can glitch if en changes while clk is high. A characterized ICG captures the gating decision with a low-transparent latch and holds it throughout the high phase. Rising-edge registration is optional control design; it alone still changes Q during the high phase.

Read it left to right: the decision is made in the OR gate, frozen by the latch, then applied by the AND gate.

• The bubble on EN makes the latch open only while clk is low, which is exactly when the AND gate's other input is 0, so changes cannot reach gated_clk.

• While clk is high the latch holds en_lat, so the AND sees a steady enable for the whole pulse.

• te joins in the OR, so scan can force the gate open whatever en says.

Model answer

The picture has four slots per clock period: two while clk is high and two while it is low. A pulse cut short shows up as one high slot instead of two. The same en drives both gates, and it changes twice while clk is high.

• Bare AND gate: in g_naive, en falls one slot into the first high phase, so the gated clock is a runt pulse. Later en rises one slot into the second high phase, so a late short pulse appears. A flop clocked by either pulse can capture at the wrong moment.

• Latch-based gate: in g_icg, the latch holds en_lat steady while clk is high. The first pulse stays full width, the late enable does nothing, and en only takes effect after clk falls.

Meet the ICG enable and test-control gating setup/hold requirements at latch closure. Low-phase capture prevents ideal-model high-phase disturbances, but does not remove physical timing obligations. An inactive/falling-edge register can be another scoped method for a positive-edge clock if the target flow supports it and its half-cycle timing is met. On FPGA, prefer supported clock-enable pins or dedicated clock-control resources. See canonical safe gating.

Every gate gets a test override that keeps scan clocks alive. Prefer one enable per functional cluster over one per flop, and review the gating against realistic activity traces.

Follow-ups

• Why the latch rather than a rising-edge flop alone? A rising-edge flop updates while clk is high. The low-transparent latch holds throughout that phase, subject to characterized closure timing. A falling-edge alternative must satisfy its own clock and enable timing; no ideal model establishes physical margin.

• What does the test input do during scan shift? It forces the gate open so shift clocks reach every flop. Without it, ATPG patterns cannot shift through gated domains.

• One enable per flop or per cluster? Per cluster. Per-flop gating explodes the enable logic and its routing, which costs more than the flops saved.

Common wrong answers

• ANDing clock and enable in RTL. Correct intent, unsafe circuit. Any enable transition during the high phase becomes a runt clock pulse.

• Ignoring enable/test timing because a latch exists. Both controls must meet the selected cell's gating checks; optional registration does not waive them.

• Skipping the scan override. The design gates fine in function and fails in test. Every gate control needs the override path.

Testbench

A behavioural ICG with scan override, a gated counter, and a bench for hold, advance, override and a mid-high enable change. Pulse width and gating margin come from implemented timing checks, not from this zero-delay model.

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`timescale 1ns/1ps
module icg (
  input  logic clk,
  input  logic en,          // intent-driven; obey the target ICG gating timing
  input  logic te,          // scan override: forces the gate open in test
  output logic gated_clk
);
  logic en_lat;
  always @(clk or en or te) begin
    if (clk == 1'b0) en_lat = en | te;   // transparent while low, holds while high
  end
  assign gated_clk = clk & en_lat;
endmodule

module gated_counter (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       en,
  input  logic       te,
  output logic [7:0] count
);
  logic gated_clk;
  icg u_icg (.clk(clk), .en(en), .te(te), .gated_clk(gated_clk));
  always @(posedge gated_clk or negedge rst_n) begin
    if (!rst_n) count <= 8'h00;
    else count <= count + 8'h01;
  end
endmodule