Senior interviews probe combinational RTL through failure modes. Each lesson supplies a model answer and finite functional checks.
4 lessons, about 14 min
Assign combinational outputs on every path, size results explicitly, and time enables with their associated data. Delaying an enable requires delaying or holding that data too; registration is not a universal requirement.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
The latch inference trap
A latch is inferred whenever a combinational output keeps its previous value on some path.
Defaults first covers incomplete if statements as well as the case; a default branch alone does not.
An intentional latch is coded as storage, never inferred by omission.
Rule of thumb: assign every output at the top of the block, then override.
Signed arithmetic and width truncation
Declare signed on the signals; the width and signedness of an expression are fixed before a cast.
An addition needs W plus one bits and a multiply needs the sum of the operand widths.
Truncation is exact only when the top two sum bits agree.
Rule of thumb: signed on the signals, full width on the result, and a flag that fires exactly on overflow.
Parameterized RTL and carry-chain guards
W + $clog2(N) bits is a safe unsigned sum width for N = 1 and for non-powers of two.
REG_OUT puts the whole addition cone before one register; it does not cut the cone.
Test full-scale vectors, and run illegal configurations as separate expected-failure jobs.
Rule of thumb: keep the full-width sum, and find the actual critical cone in the timing report.
Glitches on enables and combinational hazards
A synchronous enable only matters at the edge: a glitch that settles before setup changes nothing.
On a clock line or latch enable the same glitch is a runt edge or a transparent window.
If control is delayed, delay the data too, or hold the data through the later accepting edge.
Rule of thumb: time the enable and its data together, and gate clocks only with a characterised ICG.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Level-sensitive latch: when it is risky and how to code it safely
Practice question: Safe clock gating cell with a latch-based enable
Interview: run a mock interview on this topic
The benches were executed with Icarus Verilog 13.0 (2026-10-16) and print PASS. Latch inference, mapped arithmetic topology and physical enable/clock timing also need their respective lint and implementation reports.