Sequential interview questions test one habit: reasoning cycle by cycle. Each lesson supplies a model answer and finite functional checks under explicit edge and peer-progress assumptions.
Question | Skill under test |
|---|---|
Blocking vs non-blocking assignments | Simulation semantics and race discipline in clocked logic. |
Pipeline latency vs throughput | Naming the two numbers correctly and measuring both. |
Stalling without deadlock | Valid/ready backpressure that holds data and always makes progress. |
Enables, resets and counters | Control priority, wrap behaviour and reset style. |
4 lessons, about 19 min
No. Throughput rose (more results per second) while latency grew (more cycles per result). Lesson two measures both numbers on the same pipeline.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Blocking vs non-blocking: the race demo
An NBA evaluates its right side now and updates the destination later, so registers read old state.
Blocking assignments in clocked logic make the hardware depend on statement order.
Drive testbench inputs away from the accepting edge and observe after NBA.
Rule of thumb: non-blocking in clocked blocks, blocking in combinational blocks, and say why.
Pipeline latency vs throughput
An extra stage adds one cycle of latency and one rank of registers; steady-state throughput stays flat.
The clock can rise if the cut stage was critical, which is the only gain.
A feedback loop, such as an accumulator, cannot overlap iterations, so more stages do not help.
Rule of thumb: give both numbers with units, then say which one the change moved.
Stalling without deadlock
A stalled item keeps valid high and its data flat; a bubble is an empty slot with valid low.
The stage accepts whenever it is empty and empties whenever downstream is ready.
Valid must never wait for ready, and a long chain needs a registered-ready skid buffer.
Rule of thumb: every accepted item must leave as exactly one delivered item.
Enables, resets and counters
Priority is reset, then load, then enable; load and enable together loads.
Terminal count is high while the last value is present, not on the wrap itself.
Reset only the control state; datapath registers written before use need none.
Rule of thumb: keep the clock free-running and gate the data update with the enable.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Blocking vs non-blocking in sequential logic
Practice question: Two-stage valid/ready pipeline: throughput vs latency and backpressure
Practice question: Three-stage pipeline with stall, bubble and flush control
Code lab: Pipeline stall logic
Code lab: Counter with load
Interview: run a mock interview on this topic
The benches were executed with Icarus Verilog 13.0 (2026-10-16) and print PASS.