Clock-domain crossing and reset questions test judgment under uncertainty. Each answer names a structure, protocol assumptions and finite digital checks. Each lesson carries a self-checking bench; simulation still cannot prove analog metastability safety, physical timing bounds or system MTBF.
4 lessons, about 18 min
Whether the bits are related. Independent flags are safe. A counter or a data word needs Gray code, a handshake, or a FIFO, as the bus lesson shows.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
A CDC review: what to check
Classify first: single-bit control, multi-bit value, or data stream. The structure follows the traffic shape.
Only the second flop feeds destination logic. A source must hold a value for more than one destination period.
A false-path or clock-group exception silences timing. It does not make a crossing safe.
Rule of thumb: cross one bit with two flops, many bits with Gray code, a handshake or a FIFO, and never judge safety by the timing report alone.
Reset assertion vs release
Assertion needs no clock. Release must meet the clock, so it goes through a two-stage synchroniser.
Each clock domain gets its own reset synchroniser. Consumers use its output, never the raw reset.
Data buses that cross domains stay unreset where possible, so a reset value cannot leak across as data.
Rule of thumb: assert asynchronously, release synchronously, and give every domain its own release.
Why an async FIFO uses Gray pointers
Gray code changes one bit per step, so a sampled pointer is either the old or the new value.
A FIFO with 2^AW entries uses AW + 1 bit pointers. Equal pointers mean empty; one lap apart means full.
Compare Gray with Gray, and use the next write pointer. Stale remote pointers only delay permission.
Rule of thumb: cross a pointer that can only step by one, and compare it in the domain that owns the flag.
Pulse synchronizers and reset-domain crossings
Turn the pulse into a level with a toggle, cross it, and XOR with the previous value to rebuild one pulse.
Each toggle level must last long enough for the destination to sample it, about three clean edges for open-loop use.
Reset crossings fail by cleared data, cleared history or release order. Block acceptance and establish a fresh baseline.
Rule of thumb: never stretch a pulse blindly: toggle it or handshake it, and treat a mid-transfer reset as part of the protocol.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: A unified CDC strategy: handshake, FIFO and synchronisers
Practice question: Debugging multi-bit bus corruption without a handshake
Practice question: Debugging metastability from asynchronous reset deassertion
Code lab: Build a reset synchroniser
Code lab: Async FIFO Gray pointers
Interview: run a mock interview on this topic