“Async or sync reset, and why?” The interviewer is testing whether assertion and release are treated as separate problems.
The short answer is the hybrid: async assert for immediacy, sync deassert against metastability. Here is the reasoning behind each half.
State that must become safe without a running clock needs clock-independent assertion, commonly asynchronous assert with synchronized release. Other control/datapath state may use synchronous reset or remain unreset if validity and write-before-use prevent observation. Choose per register contract, including stopped-clock and power behavior; asynchronous reset is not mandatory on every flop.
Side | Requirement | Circuit |
|---|---|---|
Assert | Clock-independent for state requiring it | Raw reset drives reset-synchronizer stages; synchronized domain reset drives selected downstream async-reset state. |
Release | Nominally after STAGES clean local edges in the digital model | Chain shifts in 1; depth/settling and downstream recovery/removal require physical closure (template). |
Each slot is one clock cycle. The input falls and rises between clock edges, so assertion and release show as separate halves.
Slots 0 to 2: arst_n rises just before an edge. ff1 captures it at that edge, and srst_n follows one edge later, so release takes two edges.
Slot 4: arst_n falls mid-cycle and both stages already read 0 in that same slot, with no waiting edge.
Slots 6 to 7: the second release repeats the two-edge pattern, so downstream logic starts on a clock edge.
One synchroniser serves one clock domain. A second domain gets its own synchroniser from the same source, and interacting domains leave reset in dependency order (sequencing). Data buses that cross domains stay unreset where possible, so a reset value cannot leak across as fake data.
So only the release travels down the chain, one stage per clock edge. Assertion bypasses the chain through the asynchronous clear.
Two is a common starting point. Use characterized PVT parameters, implemented settling time, reset activity and the allocated reliability budget to choose depth. More stages add nominal latency and settling; no stage count guarantees an exact physical release edge.
Async assert: it forces control state to a known value at once, without waiting for the first edge. The release then waits for the clock through the synchroniser.
“One reset style everywhere.” Synchronous reset cannot act on a stopped clock, but is valid when the contract allows waiting. Unreset data is valid when it is written before use and guarded by reset validity state.
“One synchroniser shared between two clocks.” Release must align to the clock that uses it. Each domain gets its own synchroniser.
The finite digital phase sweep releases reset at nine positions between clock edges and checks nominal two-stage release. Select stage depth from characterized reliability and inspect the implemented reset tree, as in reset architecture.
// Asynchronous assert, synchronous release: one reset synchroniser per clock domain.
module reset_sync #(parameter int STAGES = 2) (
input logic clk,
input logic arst_n, // asynchronous reset input (pin, POR, or another domain)
output logic srst_n // reset for this clock domain
);
// Legal range: STAGES >= 2 (a single flop cannot give the settling the chain exists for).
if (STAGES < 2) begin : g_bad_stages
initial $fatal(1, "reset_sync: STAGES must be >= 2");
end
logic [STAGES-1:0] sr;
always_ff @(posedge clk or negedge arst_n)
if (!arst_n) sr <= '0; // assert: immediately, no clock needed
else sr <= {sr[STAGES-2:0], 1'b1}; // release: shifts in 1s, one stage per clock
assign srst_n = sr[STAGES-1];
endmodule
Phase sweep Run with Icarus Verilog 13.0 (2026-10-16): prints PASS. It releases reset at nine positions between clock edges and checks the nominal two-stage release. It does not inject analog metastability or measure recovery and removal.