This topic turns four common senior interview questions into model answers and finite RTL checks.
Decision | Rule of thumb |
|---|---|
Encoding | Compare binary and one-hot in implementation reports. Arbitrary async status needs a snapshot handshake; Gray needs an audited one-bit sequence. |
Output style | Glitch-sensitive boundary: registered output. Same-cycle local reaction: Mealy. Moore decode alone is not necessarily glitch-free. |
Proof | Show reachability, return to IDLE, and illegal-code recovery. |
Structure | The controller issues commands. The datapath owns the registers. Status flows back. |
4 lessons, about 20 min
Re-encode the state (often one-hot on FPGA) or register the outputs, then re-run STA. The report picks the encoding, not dogma.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Choosing an FSM Encoding from Timing
Write the FSM as an enum and let synthesis re-encode it; confirm in the report and re-run STA.
Do not use bit tests such as state[1] outside the FSM; export decoded flags.
A default-to-IDLE only defines RTL behaviour; recovery needs safe-FSM controls and fault checks.
Rule of thumb: the report decides the encoding, per FSM.
Moore vs Mealy Outputs
Moore depends on state alone; Mealy also depends on live inputs. Moore is not automatically registered.
A combinational Moore decode can still glitch just after an edge.
Chained Mealy outputs add up their combinational delay across the chain.
Rule of thumb: register any output whose consumer needs a glitch-free control.
Proving an FSM Correct
Reach each state through legal inputs first; forcing the state register hides reset and encoding bugs.
Liveness holds only under the assumption that an awaited response eventually arrives.
State and transition coverage back the claim; line coverage does not.
Rule of thumb: a default branch specifies RTL behaviour for unused codes, not silicon recovery.
The Controller and Datapath Split
The controller issues commands and reads only status flags; the datapath owns the data registers.
Exactly one block drives each signal, and mutually exclusive commands never assert together.
Status comparators sit on the controller's critical path, and STA must cover them.
Rule of thumb: for variable latency, poll done_o instead of counting cycles.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: One-hot vs binary encoding trade-offs and pitfalls
Practice question: Mixed encoding hazards when tools re-encode automatically
Code lab: One-hot control FSM
Practice question: FSM output encoding: registered vs combinational hazards
Code lab: Moore three-state FSM
Interview: run a mock interview on this topic
The benches were executed with Icarus Verilog 13.0 (2026-10-16) and print PASS. Timing choices use explicitly illustrative budgets; implemented fault recovery remains a separate signoff obligation.