The question

"Our STA report shows the FSM state decode on the critical path. Would you re-encode, and how?" The interviewer is testing whether the answer starts from evidence instead of habit.

A strong answer names the options, ties each to a timing or area fact, and ends with how to confirm the fix in the report.

Model answer

Binary uses fewer flops but can need deeper decode. One-hot uses one flop per state and can simplify decode, at a routing and clock-load cost. Gray changes one bit only between adjacent entries in its chosen sequence; arbitrary FSM branches, aborts and resets need not follow that sequence.

Use the platform and reports to compare candidates. For an arbitrary FSM status crossing, capture and hold a coherent status snapshot until the receiving handshake acknowledges it. Reserve Gray transfer for a constrained sequence whose every allowed transition is audited, with per-bit synchronization and physical bus-skew bounds; see encoding choice and bus crossing.

Write the RTL as an enum and let the tool re-encode it through its FSM option. Confirm the result in the synthesis report, and re-run STA.

Export decoded status rather than encoding-dependent bit tests. A default-to-IDLE specifies RTL behavior for unused codes; synthesis may re-encode or optimize that logic. If fault recovery is required, select supported safe-FSM controls, inspect extraction/encoding/recovery reports and check the implemented machine against the fault model. An enum alone does not guarantee safe implementation.

Worked encoding decision

Illustrative report inputs below are invented teaching budgets, not measured results. Assume five states, a 1.00 ns data-path budget after clock/setup terms, unchanged output latency, and room for two extra flops. Decompose total arrival before choosing.

Under those illustrative budgets, try one-hot: it fits the flop allowance and preserves latency while recovering setup margin. Validate extracted encoding, all setup/hold views, route/fanout and power before accepting it. A routed one-hot net delay above 0.65 ns would erase this margin and reopen the choice. The transition bench below checks function, not this timing decision.

Follow-ups

• STA still fails after one-hot. What next? Register the FSM outputs or split the decode across a pipeline stage. Encoding is one lever among several.

• Why not hand-write one-hot codes? Hand codes lock the encoding into the RTL. An enum keeps the logic unchanged while the tool tries each encoding.

• The tool re-encoded the enum. How is that confirmed? Inspect the extracted FSM and final encoding in the synthesis report. The functional named-status checks can be reused if the status mapping is preserved; the internal forced-code injection must be rebuilt for the actual implementation encoding and fault model.

Common wrong answers

• "One-hot is always faster." On a tiny FSM the extra flops and routing cost more than the decode saves. The report decides, per FSM.

• "Reset proves fault recovery." The default defines unused-code RTL behavior only. Supported safe-FSM controls and implemented fault-injection checks are needed for a recovery requirement.

• "Gray fixes any state crossing." Branches and aborts can change multiple bits. An arbitrary state needs a stable snapshot handshake; an audited Gray sequence still needs synchronizers and physical bounds.

Testbench

The bench reaches five states, checks 20 state/input combinations, and injects unused codes 5–7. The named state_o mapping preserves the functional observations, but the internal fault injection is specific to this RTL encoding.

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// State codes are named once, above the design, so the testbench can reuse them.
typedef enum logic [2:0] {IDLE, LOAD, RUN, WAIT, DONE} state_t;

module burst_ctrl (
  input  logic       clk, rst_n, start, ready,
  output logic       active, done_o,
  output logic [2:0] state_o
);
  state_t state, next_state;

  always_comb begin
    next_state = state;
    active = 1'b0;
    done_o = 1'b0;
    case (state)
      IDLE: if (start) next_state = LOAD;
      LOAD: begin next_state = RUN; active = 1'b1; end
      RUN:  begin active = 1'b1; if (ready) next_state = DONE; else next_state = WAIT; end
      WAIT: begin active = 1'b1; if (ready) next_state = DONE; else next_state = WAIT; end
      DONE: begin next_state = IDLE; done_o = 1'b1; end
      default: next_state = IDLE;
    endcase
  end

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) state <= IDLE;
    else        state <= next_state;

  // Named-state readout for the testbench: literals only, so no enum-to-vector cast.
  always_comb begin
    case (state)
      IDLE: state_o = 3'd0;
      LOAD: state_o = 3'd1;
      RUN:  state_o = 3'd2;
      WAIT: state_o = 3'd3;
      DONE: state_o = 3'd4;
      default: state_o = 3'd7;
    endcase
  end
endmodule

Related topics

• Choosing an encoding

• Illegal states and recovery