“Nominal timing is clean but the corner run fails. What do you do?” A second part asks what STA checks on a clock-gated domain.
The question tests sign-off judgement. Nominal is one point in a space of voltage, temperature, and process.
Low voltage often slows cells, but the temperature dependence is library-specific and can invert. Cell, wire and clock delays do not scale identically. Slow/setup and fast/hold are useful starting intuitions, not exclusive signoff targets.
Run setup and hold across every mandated process, voltage, temperature, RC and operating-mode view. Model on-chip variation with the flow's early/late derates or statistical models; clock uncertainty separately budgets jitter and other specified clock margins.
Corner | Condition | Closes which check |
|---|---|---|
Slow cell views | Approved slow libraries, voltages, temperatures and RC combinations | Often setup-limiting; check hold too |
Fast cell views | Approved fast libraries and their RC combinations | Often hold-limiting; check setup too |
Typical (TT) | Nominal models | Reference or required analysis view; never a substitute for the signoff matrix |
Clock gating adds its own check. The enable must arrive with setup and hold margin against the clock at the gating cell, in both test and mission mode. For a library ICG cell, many tools time the enable through the cell's own library setup/hold arcs; set_clock_gating_check margins may apply only to gating inferred on combinational cells. Check your tool's documentation and confirm in the report which check type was applied.
Read each row against the clock edges above it. The highlighted box is the time the enable may not move.
AND gate: an enable change anywhere in the high phase cuts or adds a clock pulse, so the window spans the whole high phase plus the 0.05 margins from the SDC below.
ICG cell: the latch is closed while the clock is high, so the enable only has to meet the cell's own setup and hold around the rising edge.
Both windows must be met in every mode where the gate is active, including test mode.
# SDC template: adapt the enable pin name to the selected library cell.
set icg_enable [get_pins u_icg/en]
if {[sizeof_collection $icg_enable] != 1} {
error "Expected exactly one ICG enable pin"
}
set_clock_gating_check -setup 0.05 -hold 0.05 $icg_enable
# Load in each applicable mission/test analysis view with that view's
# clocks and test-mode case analysis. Collection APIs vary by STA tool.Q: Setup passes at TT but fails at SS by 0.2 ns. RTL change or ECO? Start with the report split. If a few cells dominate the corner spread, swap Vt or upsize them (ECO). If the path has too many logic levels at every corner, restructure or pipeline. If net/RC delay dominates, fix placement or buffering.
Q: Is clock uncertainty a substitute for on-chip variation modeling? No. Use the approved derates or AOCV/POCV models for relative path variation, and uncertainty for specified clock jitter and margins. Inspect reports to avoid double-counting the same allowance.
Q: The gating enable comes from far away and misses its check. What is the fix? Register the enable near the gating cell so the check sees a short local path, if the enable can be generated one cycle earlier or the extra gating latency is acceptable to the gated logic; otherwise move or duplicate the enable logic and fix placement. A long enable wire is a placement problem first.
“Add margin by over-constraining the clock.” Hidden margin distorts every downstream fix. State uncertainty explicitly instead.
“Gate the clock with an AND gate in RTL.” An AND gate can glitch. Use a library gating cell with an enable check.
“Test mode needs no gating check.” Scan enable is commonly held during shift and changed for capture; it need not toggle every cycle. Analyze the actual test clocks, override controls and legal shift/capture transitions, including applicable gating checks.
No. Fix the reported minimum-delay or clock-skew problem, then recheck setup and hold across all required views. A passing slow view does not waive another view's failure.
The test-mode check. Shift activity exercises the enable differently, so the check must pass with the test override active.