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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
    • STA Foundations
      • Where RTL Meets STA
      • Canonical STA Flow
      • Corners
      • SDC Starter Set
      • Why RTL Architecture Dominates
    • Setup, Hold and Slack
    • Skew and Variation
    • Timing Exceptions
    • Clock Gating
    • RTL for Timing
    • Clock Architecture
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹STA Foundations
  1. Topics
  2. RTL Design
  3. Timing & Clocking
  4. STA Foundations
  5. Corners

Part 5 · Timing & Clocking · Intermediate

Corners

Slow/fast corner intuition and setup, hold, recovery and removal across every required signoff view.

On this page

    Why this matters

    A path that meets timing at one process, voltage and temperature can fail at another. A hold failure in a slow view or a setup failure in a fast view is easy to dismiss and real.

    After this lesson you can: explain why signoff checks several corners and modes, show with a scale factor how the path delay changes, and compute a minimum period from a path's terms.

    Delay is not a single number

    A gate delay depends on manufacturing process, supply voltage and temperature. Signoff therefore checks several corners.

    Slow data often limits setup and fast data often limits hold. These are starting intuitions: relative clock/data delays, RC corners and library checks decide the actual worst view.

    Corner

    Process / voltage / temperature (typical)

    Gates are

    Used for

    Slow

    Slow process, low voltage; temperature from the library view

    Usually slow data

    Often limits setup; also check hold, recovery and removal

    Fast

    Fast process, high voltage; temperature from the library view

    Usually fast data

    Often limits hold; also check setup, recovery and removal

    Typical

    Nominal

    Nominal

    Power estimates, sanity checks

    A numeric picture

    Consider a 1.00 ns typical path with illustrative scale factors. The factors only show the effect; real libraries give different numbers.

    Corner

    Scale factor

    Path delay

    Effect

    Fast

    × 0.70

    0.70 ns

    Shortest delay → hold is hardest

    Typical

    × 1.00

    1.00 ns

    Reference

    Slow

    × 1.35

    1.35 ns

    Longest delay → setup is hardest

    setup slackslow​=T−(tcq​+tlogic​+tsu​)slow​hold slackfast​=(tcq​+tlogic​)fast​−thold​

    Put that path in a 1.50 ns cycle with 0.12 ns setup, 0.06 ns hold and no skew or uncertainty. Count its delay from the launch edge to the D pin, clock-to-Q included.

    One path at three corners. Each bar ends when the new data arrives: 0.70 ns fast, 1.00 ns typical, 1.35 ns slow. The shaded strips are the hold window after the launch edge (to 0.06 ns) and the setup window before the next edge (from 1.38 ns).

    Read each bar as the time the new data takes to reach the capture flop. A bar must end after the hold strip and before the setup strip.

    • Slow corner: the bar ends at 1.35 ns, only 0.03 ns before the setup window at 1.38 ns. Setup is tightest here.

    • Fast corner: the bar ends at 0.70 ns, the closest of the three to the hold strip: hold slack 0.70 - 0.06 = +0.64 ns. Hold is tightest here.

    • Typical sits in between and is the tightest at neither check, which is why signoff never uses it alone.

    Corner

    Arrival

    Setup slack (1.38 - arrival)

    Hold slack (arrival - 0.06)

    Fast

    0.70 ns

    +0.68 ns

    +0.64 ns (worst hold)

    Typical

    1.00 ns

    +0.38 ns

    +0.94 ns

    Slow

    1.35 ns

    +0.03 ns (worst setup)

    +1.29 ns

    Corners also include RC corners for the wires (high or low resistance and capacitance) and, in modern flows, many combinations (multi-mode multi-corner, MMMC). Every mode (functional, test, sleep) is checked at every relevant corner.

    Common mistakes

    Common pitfall

    Do not discard a hold failure in a slow view or a setup failure in a fast view. Clock and data paths scale differently. Temperature inversion can also make cold silicon slower at low voltage. Check both delay directions and recovery/removal in every mandated library/RC/mode view, including both temperature extremes where required. A fix must preserve all of them.

    Check yourself Data is 20 ps faster in view B, but the capture clock is 80 ps later than in view A. Can hold be worse in B?

    Yes. Holding the other terms fixed, hold slack changes by -20 - 80 = -100 ps. The corner name alone does not determine the worst check.

    Interview

    “Why can you fix a hold violation without changing the clock frequency, but not a setup violation?” For a full-cycle, same-edge register path, hold compares data against the same clock edge, so it is independent of the period; setup depends on the period. Slowing the clock fixes setup but not that hold check. Opposite-edge (half-cycle) paths and multicycle paths without a matching hold exception do have a hold check that moves with the period.

    Check yourself At the slow corner a path takes 1.35 ns plus 0.12 ns setup and 0.35 ns clock-to-Q. What is the shortest clock period that passes setup?

    T ≥ 0.35 + 1.35 + 0.12 = 1.82 ns, i.e. about 549 MHz, ignoring skew and uncertainty.

    Remember

    • Gate delay depends on process, supply voltage and temperature, and wires add RC corners.

    • Slow data often limits setup and fast data often limits hold, but the relative clock and data delays decide the worst view.

    • Check every mode (functional, test, sleep) at every relevant corner.

    Rule of thumb: do not discard a hold failure in a slow view or a setup failure in a fast view.

    Keep going

    • Interview: run a mock interview on this topic

    Related topics

    • SDC starter set

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    See also

    • Where RTL Meets STA
    • Why RTL Architecture Dominates