STA breaks the design into timing paths. Each path runs from a startpoint to an endpoint.
A startpoint is a flip-flop clock pin or an input port. An endpoint is a flip-flop data pin or an output port.
Combinational logic and wire sit in between.
Path type | Startpoint | Endpoint | Governed by |
|---|---|---|---|
Register to register | Flip-flop clock pin | Flip-flop D pin | The clock period |
Input to register | Input port | Flip-flop D pin |
|
Register to output | Flip-flop clock pin | Output port |
|
Input to output | Input port | Output port | Both input and output delays (a purely combinational feed-through) |
RTL structure sets what each path contains. The table lists the main effects.
RTL feature | Effect on timing |
|---|---|
Registers between logic | Cut the design into paths. More registers mean shorter paths. |
Combinational depth between registers | Directly sets path delay. |
Fanout of a signal | More loads mean slower transitions and extra buffers. |
Muxes and enables on D inputs | Add logic in front of every register. |
Combinational feed-through from input to output | Creates input-to-output paths that most designs prefer to avoid. |
Multiple clocks | Paths between clocks need explicit handling (CDC and exceptions). |
A quick proxy is the longest topological path in the flattened combinational graph. Yosys ltp -noff excludes flip-flop cells; it does not select only register-to-register paths. An output-only registered adder can instead have an input-port-to-register-D path. Inspect the printed start/end nets and map them back to ports or register pins.
For a bounded experiment, save the design modules (exclude tb_ks) and the two matching measurement tops from Architecture dominates as design.sv. Both tops register inputs and outputs; their arithmetic path is from ra/rb Q to the output register D (y in the plain top, u.r in the prefix top). Record the source revision, Yosys version, bundled ABC version/banner and complete logs for both fresh runs:
yosys -V
yosys -p "read_verilog -sv design.sv; synth -top measure_plain -flatten -noabc; abc -g AND,OR,XOR,MUX; stat; ltp -noff"
yosys -p "read_verilog -sv design.sv; synth -top measure_prefix -flatten -noabc; abc -g AND,OR,XOR,MUX; stat; ltp -noff"Design (registered output) | Levels in the longest path |
|---|---|
8-bit adder | 15 |
16-bit adder | 31 |
32-bit adder | 63 |
32-bit comparator ( | 20 |
8×8 multiplier | 30 |
8×8 multiply-add ( | 33 |
These are generic-flow counts. The commands above define a comparison with explicit tops, and another tool version can give different counts. Generic cells are not library area, and levels are not nanoseconds. Real tools use a cell library with timing-driven optimisation.
The reported adder counts grow roughly linearly with width in that mapping. The + operator does not require ripple carry; another mapper, library or timing target can choose a different carry structure. See the Yosys ltp reference for the command's graph scope.
About (2.0 − 0.5) / 0.1 = 15 levels under that assumed cost; real cell and wire delays change the number. The 8-bit adder above (15 levels) just fits; the 16-bit adder (31 levels) would need to be restructured or pipelined.
The level counts in the table are historical generic-flow counts. The original source bundle and tool and ABC versions were not recorded. Only the 32-bit adder row was re-run (Yosys 0.69, 2026-10-16, measure_plain), and it gives 63 levels, matching the table.