Dynamic power includes clock-pin and internal-node activity. A flop whose Q stays constant can still consume dynamic power while its clock toggles. Clock gating removes clock activity downstream of the gate; a data enable alone does not necessarily do that. Leakage remains even when switching stops.
The first step is intent: name the cycles with no useful work. Three common sources are listed below.
Idle state: the block has nothing to do until the next request.
Empty FIFO: no data to consume or no space to produce into.
Stalled pipeline: downstream backpressure freezes progress for a cycle.
A latch-based gate passes the clock only while the enable holds. The diagram samples each rising edge of clk.
The cycle-sampled view explains state, not pulse shape: adjacent active slots can appear continuously high. The event trace below assumes a 10 ns period and 5 ns high phase, initially disabled.
Time (ns) | clk / en | Raw AND | Low-latch ICG |
|---|---|---|---|
5, rising edge | 1 / 0 | 0 | 0; latched enable = 0 |
7, enable rises during high | 1 / 1 | Rises late: 3 ns runt pulse | Stays 0; latch closed |
10, falling edge | 0 / 1 | Falls | Latch opens and records 1 |
15, rising edge | 1 / 1 | Rises | Rises: full pulse begins |
17, enable falls during high | 1 / 0 | Falls early: 2 ns runt pulse | Stays 1; latch closed |
20, falling edge | 0 / 0 | 0 | Falls after full 5 ns pulse; latch records 0 |
25, rising edge | 1 / 0 | 0 | 0 |
Watch gated_clk: it copies clk only while en is high, and q moves only on gated edges.
Slot 0: en is 0, the gate is shut, and q holds 0.
Slot 1: en is still 0, and q is still 0.
Slot 2: en is 1, the first gated edge arrives, and q goes to 1.
Slot 3: en is still 1, the second gated edge arrives, and q goes to 0.
Slot 4: en is 0, the gate is shut, and q holds 0.
Slot 5: en is still 0, and q is still 0.
Write a plain enable on a normal register and let the flow map it to a library ICG cell. That keeps the RTL portable across technologies.
Instantiate a cell only for gates that need special handling, such as a scan override. Never gate with raw AND logic in RTL.
Style | Use | Risk |
|---|---|---|
Plain enable with | Portable functional intent | Verify mapping to a mux, clock-enable pin or ICG; review gating timing and test control |
Instantiated ICG cell | Scan override or cells with test pins | Locks the RTL to one library |
Raw | Never | Glitchy edges with no test path |
A raw AND can shorten the pulse or introduce an extra edge. The ICG's low-transparent latch is closed during the high phase, so that change waits for the next low phase. A rising-edge enable register alone does not provide this protection.
The latch follows the enable while the clock is low and freezes before the rising edge. That keeps the gate output stable across the edge, so no runt pulse forms.
The latch-based gate and directed checker compare every active capture and every idle observation.
`timescale 1ns/1ps
module icg_model (
input logic clk, en,
output logic gated_clk
);
logic en_lat;
initial en_lat = 1'b0;
// Latch is transparent while clk is low, frozen while clk is high.
always @(clk or en) if (!clk) en_lat = en;
assign gated_clk = en_lat & clk;
endmodule
module gated_reg (
input logic gated_clk, rst_n,
input logic [7:0] d,
output logic [7:0] q
);
always_ff @(posedge gated_clk or negedge rst_n) begin
if (!rst_n) q <= 8'h00;
else q <= d;
end
endmodule
The event-trace table is illustrative, not a measured waveform.
The latch-based gate and directed checker compare every active capture and every idle observation. This digital model does not check library gating timing or physical pulse widths.