Gate control usually comes from status signals that can glitch. A flop on the enable moves every change to just after the rising edge.
A rising-edge enable register changes while the clock is high. The ICG latch, not the register alone, prevents this change from disturbing the current pulse. The latch follows during the next low phase and must close with its setup/hold requirements met. Registration is a control-design choice, not a replacement for the ICG.
Each slot is half a clock period, numbered from 0: even slots are just after a rising edge, odd slots just after a falling edge. run_i is the raw request, en_q the enable flop, lat the ICG latch, and gclk the gated clock.
Slot 1: the raw request glitches high between two rising edges. At slot 2 en_q is still 0, because the flop only samples at a rising edge.
Slot 3 and 4: the real request is high, so en_q rises just after the rising edge in slot 4 (E0). The latch is closed while the clock is high, so there is no gated pulse yet.
Slot 5 and 6: in the low phase the latch takes en_q = 1. The next rising edge (E1, slot 6) gives the first full gated pulse.
Slots 9 to 11: the request drops, yet the edge in slot 10 still passes a full pulse. en_q clears after it, and the latch closes the gate in slot 11.
Scan shift needs clocks while functional enables rest. OR-ing a test override into the latch keeps gated domains controllable in test mode.
Every gate gets the override. A domain without one cannot shift, so coverage falls exactly where gating was densest.
Share gates among registers with compatible enables. Independently idle subgroups can save more switching with finer gates, but added ICG, control and clock-tree capacitance can offset the benefit. Compare activity-weighted capacitance, area, clock skew and gating timing in mapped/routed results.
Prefer one enable per functional cluster, not per flop.
Include scan and test override in every gate control.
Review gating chances against realistic activity traces.
The enable flop only samples at the rising edge, so the pulse is gone before it matters. The latch then sees a settled enable for the whole low phase.
Their values from before the idle window. With no gated edge, no flop in the cluster can change, so all four hold.
This is a same-clock capture interface, not valid/ready. Acceptance occurs only at a gated rising edge with reset released. The producer holds the first word through wake-up and each accepting edge; scan captures are counted separately from functional work. Shutdown requests stop new offers only after the final acceptance; the control register permits one final full clock pulse.
Event | Control / gate | Data ownership |
|---|---|---|
Falling edge before E0 | Request run; en_q still 0 | Offer word 0 and hold |
E0 rising | en_q becomes 1 after edge; no gated edge | Word 0 still pending |
Next low phase | ICG latch takes en_q = 1 | Continue holding word 0 |
E1 rising | First full gated pulse | Capture word 0; advance only afterward |
Falling edge before last capture | Request idle | Hold final word |
Last rising edge | Old latched enable passes pulse; en_q clears | Final capture completes |
Next low phase | Latch closes gate for following rising edge | No pending word may be discarded |
`timescale 1ns/1ps
module gate_ctrl (
input logic clk, rst_n, idle_i, block_active_i,
output logic en_q
);
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) en_q <= 1'b0;
else en_q <= !idle_i && block_active_i;
end
endmodule
module safe_icg (
input logic clk, en_q, te_i,
output logic gclk
);
logic lat;
initial lat = 1'b0;
// Test override joins inside the latch so scan clocks run while enables rest.
always @(clk or en_q or te_i) if (!clk) lat = en_q | te_i;
assign gclk = lat & clk;
endmodule
module gated_nib (
input logic gclk, rst_n,
input logic [3:0] next_s,
output logic [3:0] state_q
);
always_ff @(posedge gclk or negedge rst_n) begin
if (!rst_n) state_q <= 4'h0;
else state_q <= next_s;
end
endmodule