The question

The interviewer asks: a master reads an address nobody owns and gets OKAY with garbage data. Software then spins on a fake status bit for a week. What is broken, and what should the fabric have done?

This tests map completeness. Every address must hit exactly one slave or the default slave, and the default slave must answer with an error, never with OKAY. Fabric-level holes return DECERR (or a documented error); reserved offsets inside a slave follow that slave's documented policy, often SLVERR or RAZ/WI (read-as-zero, write-ignored).

Model answer

A decoder turns each address into exactly one select. Addresses outside every region route to a default slave, which returns an error response so the bug surfaces on the first access instead of in the field.

Read the bar from the top: each band is one select, and the bands together cover all 256 addresses with no gap.

• The two named regions cover only 32 of 256 addresses. The default slave owns the other 224.

• Its response is AXI DECERR; a private bus may use its documented error flag. Never silent OKAY or a hang.

• Adding a slave carves a band out of the default region. The default arm itself never goes away.

For AXI, an interconnect that cannot decode an address returns DECERR, commonly through a default slave. A selected slave reports its own access failure as SLVERR. The small decoder below is a private-bus illustration with a Boolean signal named slverr, not an AXI BRESP/RRESP implementation. The flag keeps the name slverr, but for an unmapped address it stands for what AXI calls DECERR; an AXI adapter must preserve the distinction.

Private-bus contract here: one request at a time, address held while req is high; done = ack || slverr. Exactly one completion flag is asserted for each active request, ack for success and slverr for error. The master samples done at a rising edge and drops req before the next edge. This combinational decoder completes in one sampled edge; it is not a pipelined AXI slave.

Keep one central map. Decoding independently in each slave invites gaps and overlaps, and a gap that returns OKAY with garbage is the failure in the question.

Follow-ups

In an AXI adapter, register or buffer the error response according to AXI interface timing and hold its valid/payload through acceptance. The private combinational decoder below instead has an explicitly single-edge completion contract.

A watchdog reports missing progress, but cannot cancel accepted downstream work by itself. Stop new admission, retain ownership of the original transaction, and drain/quarantine late responses or use coordinated reset before slot reuse. Track accepted = delivered + cancelled + outstanding, where cancellation requires the recovery contract. See Error paths and timeouts for late-response recovery and the preceding AXI lesson for write-response dependencies.

Two regions claim the same address. Priority order in one decoder, with an assertion that the regions never overlap. Overlapping selects mean two slaves drive the response.

Common wrong answers

Return OKAY with zeros for holes. Zeros look like valid idle status, so drivers spin or misconfigure. The error response exists precisely for this case.

Hang the transfer until software is fixed. A hung transfer locks every master behind the same fabric. Errors propagate; hangs accumulate.

Let each slave decode its own range. Independent decoders drift apart across edits. One map, one decoder, one default.

Testbench

A decoder with a default-slave error arm, plus a testbench that sweeps all 256 addresses and checks every select and response.

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`timescale 1ns/1ps
module bus_decode (
  input  logic       req,
  input  logic [7:0] addr,
  output logic       sel_ram, sel_uart, ack, slverr
);
  always_comb begin
    sel_ram = 1'b0; sel_uart = 1'b0; ack = 1'b0; slverr = 1'b0;
    if (req) begin
      case (addr[7:4])
        4'h0:    begin sel_ram = 1'b1; ack = 1'b1; end
        4'h1:    begin sel_uart = 1'b1; ack = 1'b1; end
        default: begin slverr = 1'b1; end              // default slave: error, never OKAY
      endcase
    end
  end
endmodule

Related topics

• Bus integration

• AXI-Lite