AXI4-Lite is a simple memory-mapped bus: five channels, one data beat per transaction, no bursts. A master writes registers through an address channel, a data channel and a response channel, and reads them through an address channel and a data channel.
Channel | Carries | Direction |
|---|---|---|
AW (write address) | Write address | Master to slave |
W (write data) | Write data and byte strobes | Master to slave |
B (write response) | Write response: OKAY, SLVERR or DECERR | Slave to master |
AR (read address) | Read address | Master to slave |
R (read data) | Read data and response | Slave to master |
Read each arrow as one handshake: valid and the payload travel in the arrow's direction, and ready comes back.
Write: two arrows out (AW, W) and one back (B). The slave answers on B only after it holds both halves.
Read: one arrow out (AR) and one back (R). The read data and its response travel together.
Responses ride on the return arrows only: BRESP for writes, RRESP for reads.
Every transaction moves exactly one beat, so there are no length, size or burst signals. There are no IDs either, so ordering rules stay trivial: the slave in this topic handles one outstanding transaction per channel.
Full AXI4 is out of scope here: bursts, IDs, exclusive access, and reordering belong to that protocol, not to AXI4-Lite.
5 lessons, about 29 min
Either order is allowed: AW and W are independent channels. The slave updates the register only after it has captured both the address and the data, then it answers on B.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Channel Overview
Writes use AW, W and B. Reads use AR and R. Each is its own valid/ready handshake.
Latch whichever write half arrives first, wait for the other, and commit once when both are held.
A write ends with the B handshake and a read with the R beat. Valid and payload stay stable until the handshake edge.
A Minimal AXI-Lite Slave
aw_seen and w_seen latch independently, and both clear when the pair commits and B is raised.
s_arready = !s_rvalid allows one outstanding read.
A read of a register written on the same edge captures the old value. That is this bank's policy, not an AXI rule.
Rule of thumb: answer SLVERR for an unmapped word. OKAY with junk data tells software the access worked.
Responses, Strobes and Errors
A strobe bit enables its byte lane. With 0x12345678, data 0xAABBCCDD and strobes 4'b1010, the register becomes 0xAA34CC78.
A mapped slave answers SLVERR for a word in its range that selects nothing. The interconnect answers DECERR when no slave matches.
AXI4-Lite has no exclusive access, so it never returns EXOKAY. Zero strobes change no byte but still return a response.
Throughput and Backpressure
A write needs a capture edge, a commit edge that raises BVALID, and a clearing edge: three edges. A read needs a capture and a clearing edge: two.
Three limits serialise everything: one outstanding transaction per channel, no staging while a response is pending, and the AW/W pairing wait.
A faster slave can queue and pipeline, but responses must stay in order.
AXI-Lite End to End into a CSR
A beat accepted with VALID and READY belongs to the slave: hold it in a flag until its partner arrives, then commit once.
In this slave the CSR changes on the edge that raises BVALID, and a read returns the value from before its AR handshake edge.
The slave owns the protocol and turns CSR errors into SLVERR; the CSR block owns strobes, W1C, read-only and set-wins.
Rule of thumb: pair first, commit once, answer every access: an unmapped word gets SLVERR, never silence.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: AXI4-Lite slave interface with read/write register access
Code lab: AXI-lite write channel stub
Practice question: AXI4-Lite slave read interface: RTL and coverage closure
Code lab: AXI-lite read channel stub
Practice question: AXI4 write channel with WSTRB support
Interview: run a mock interview on this topic