AXI4-Lite teaches the five independent channel handshakes. Full AXI4 keeps those rules and adds burst geometry, IDs, multiple outstanding transactions, ordering, exclusives, and significantly more bookkeeping.
The worked design is an intentionally limited read master: aligned INCR bursts, one configured ID, at most four outstanding requests, no reordering, and a 4 KB boundary check. Every lesson identifies the state needed for that subset before discussing broader protocol options.
Read the stack from the bottom up: the handshakes never change, and each row adds bookkeeping on top.
The base stays. Every channel still uses the AXI-Lite valid/ready rules.
The worked design is the shaded part. It needs a beat counter, one ID check, and a four-entry queue with credits.
The dashed rows are the expensive ones. Reordering and exclusives add per-ID and per-address state, so they come last.
Added feature | RTL state it requires |
|---|---|
INCR/FIXED/WRAP bursts | Beat counter, address progression, 4-KB boundary checks, WLAST/RLAST |
IDs | Per-ID transaction context and response tagging |
Multiple outstanding | Request queues, credits, response matching |
Read reordering | Per-ID ordering plus inter-ID completion policy |
Write response tracking | AW/W association and one B response per burst |
Exclusive access in AXI4 | Exclusive monitor and fail/succeed response policy |
Atomic transactions in later AXI extensions | Operation decode, serialization, and read-modify-write response handling |
Base AXI4 defines exclusive accesses but not the protocol-level atomic transactions introduced by later AXI extensions. Keep those features separate in the support matrix instead of implying that an AXI4 component must implement AXI5 atomic operations.
Where four contexts live. With this one-ID subset, RID validates the configured stream; it cannot distinguish the contexts. An ordered context FIFO selects its head until the final accepted R beat retires that burst and returns one credit.
2 lessons, about 6 min
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
AXI4 RTL Ownership Checklist
Enqueue a burst context only on ARVALID && ARREADY, and reserve queue space before offering AR.
Outstanding = accepted AR bursts minus retired R bursts. The beat counter advances only on an accepted R beat.
An unexpected RID, length or RLAST is a protocol fault to contain, not a reason to switch contexts.
Rule of thumb: state the subset, the depths and the ordering model before you claim compliance.
Study and Implementation Path
Start with aligned INCR reads, one ID and four outstanding transactions.
AXI4 has no WID: W bursts follow AW order, and AW may follow W. Buffer early W data and issue B after AW and the final W.
Add IDs or out-of-order completion only after the ordering scoreboard and liveness properties pass.
Rule of thumb: add one concurrency feature at a time, with evidence for each new ordering state.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: AXI4 read channel with outstanding read transactions
Practice question: AXI4 read channel: RTL and read data flow verification
Code lab: AXI-Lite read channel stub
Interview: run a mock interview on this topic